pagetable.hh revision 6378:4a2ff62c3b4f
19850Sandreas.hansson@arm.com/* 29850Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 39850Sandreas.hansson@arm.com * Copyright (c) 2007 MIPS Technologies, Inc. 49850Sandreas.hansson@arm.com * All rights reserved. 59850Sandreas.hansson@arm.com * 69850Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 79850Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 89850Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 99850Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 109850Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 119850Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 129850Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 139850Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 149850Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 159850Sandreas.hansson@arm.com * this software without specific prior written permission. 169850Sandreas.hansson@arm.com * 179850Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 189850Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 199850Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 209850Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 219850Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 229850Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 239850Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 249850Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 259850Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 269850Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 279850Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 289850Sandreas.hansson@arm.com * 299850Sandreas.hansson@arm.com * Authors: Nathan Binkert 309850Sandreas.hansson@arm.com * Steve Reinhardt 319850Sandreas.hansson@arm.com * Jaidev Patwardhan 329850Sandreas.hansson@arm.com */ 339850Sandreas.hansson@arm.com 349850Sandreas.hansson@arm.com#ifndef __ARCH_MIPS_PAGETABLE_H__ 359850Sandreas.hansson@arm.com#define __ARCH_MIPS_PAGETABLE_H__ 369850Sandreas.hansson@arm.com 379850Sandreas.hansson@arm.com#include "arch/mips/isa_traits.hh" 389850Sandreas.hansson@arm.com#include "arch/mips/utility.hh" 399850Sandreas.hansson@arm.com#include "arch/mips/vtophys.hh" 409850Sandreas.hansson@arm.com#include "config/full_system.hh" 419850Sandreas.hansson@arm.com 429850Sandreas.hansson@arm.comnamespace MipsISA { 4312109SRekai.GonzalezAlberquilla@arm.com 4412104Snathanael.premillieu@arm.comstruct VAddr 459850Sandreas.hansson@arm.com{ 469850Sandreas.hansson@arm.com static const int ImplBits = 43; 479850Sandreas.hansson@arm.com static const Addr ImplMask = (ULL(1) << ImplBits) - 1; 489850Sandreas.hansson@arm.com static const Addr UnImplMask = ~ImplMask; 4913556Sgabeblack@google.com 5013556Sgabeblack@google.com VAddr(Addr a) : addr(a) {} 5113556Sgabeblack@google.com Addr addr; 529920Syasuko.eckert@amd.com operator Addr() const { return addr; } 5313556Sgabeblack@google.com const VAddr &operator=(Addr a) { addr = a; return *this; } 5412104Snathanael.premillieu@arm.com 559850Sandreas.hansson@arm.com Addr vpn() const { return (addr & ImplMask) >> PageShift; } 5612109SRekai.GonzalezAlberquilla@arm.com Addr page() const { return addr & Page_Mask; } 5712109SRekai.GonzalezAlberquilla@arm.com Addr offset() const { return addr & PageOffset; } 5812109SRekai.GonzalezAlberquilla@arm.com 5912109SRekai.GonzalezAlberquilla@arm.com Addr level3() const 6012109SRekai.GonzalezAlberquilla@arm.com { return MipsISA::PteAddr(addr >> PageShift); } 6112109SRekai.GonzalezAlberquilla@arm.com Addr level2() const 6212109SRekai.GonzalezAlberquilla@arm.com { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); } 6312109SRekai.GonzalezAlberquilla@arm.com Addr level1() const 6412109SRekai.GonzalezAlberquilla@arm.com { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); } 659850Sandreas.hansson@arm.com}; 669850Sandreas.hansson@arm.com 679850Sandreas.hansson@arm.com// ITB/DTB page table entry 68struct PTE 69{ 70 Addr Mask; 71 Addr VPN; 72 uint8_t asid; 73 74 bool G; 75 76 /* Contents of Entry Lo0 */ 77 Addr PFN0; // Physical Frame Number - Even 78 bool D0; // Even entry Dirty Bit 79 bool V0; // Even entry Valid Bit 80 uint8_t C0; // Cache Coherency Bits - Even 81 82 /* Contents of Entry Lo1 */ 83 Addr PFN1; // Physical Frame Number - Odd 84 bool D1; // Odd entry Dirty Bit 85 bool V1; // Odd entry Valid Bit 86 uint8_t C1; // Cache Coherency Bits (3 bits) 87 88 /* 89 * The next few variables are put in as optimizations to reduce 90 * TLB lookup overheads. For a given Mask, what is the address shift 91 * amount, and what is the OffsetMask 92 */ 93 int AddrShiftAmount; 94 int OffsetMask; 95 96 bool Valid() { return (V0 | V1); }; 97 void serialize(std::ostream &os); 98 void unserialize(Checkpoint *cp, const std::string §ion); 99}; 100 101}; 102#endif // __ARCH_MIPS_PAGETABLE_H__ 103 104