mt.hh revision 9918
14661Sksewell@umich.edu/*
25268Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc.
35268Sksewell@umich.edu * All rights reserved.
44661Sksewell@umich.edu *
55268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without
65268Sksewell@umich.edu * modification, are permitted provided that the following conditions are
75268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright
85268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer;
95268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright
105268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the
115268Sksewell@umich.edu * documentation and/or other materials provided with the distribution;
125268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its
135268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from
145268Sksewell@umich.edu * this software without specific prior written permission.
154661Sksewell@umich.edu *
165268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
175268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
185268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
195268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
205268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
215268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
225268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
235268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
245268Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
255268Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
265268Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
275222Sksewell@umich.edu *
285254Sksewell@umich.edu * Authors: Korey Sewell
294661Sksewell@umich.edu */
304661Sksewell@umich.edu
314661Sksewell@umich.edu#ifndef __ARCH_MIPS_MT_HH__
324661Sksewell@umich.edu#define __ARCH_MIPS_MT_HH__
334661Sksewell@umich.edu
344661Sksewell@umich.edu/**
354661Sksewell@umich.edu * @file
364661Sksewell@umich.edu *
374661Sksewell@umich.edu * ISA-specific helper functions for multithreaded execution.
384661Sksewell@umich.edu */
394661Sksewell@umich.edu
408229Snate@binkert.org#include <iostream>
418229Snate@binkert.org
424661Sksewell@umich.edu#include "arch/mips/faults.hh"
436329Sgblack@eecs.umich.edu#include "arch/mips/isa_traits.hh"
444661Sksewell@umich.edu#include "arch/mips/mt_constants.hh"
456376Sgblack@eecs.umich.edu#include "arch/mips/pra_constants.hh"
466329Sgblack@eecs.umich.edu#include "arch/mips/registers.hh"
474661Sksewell@umich.edu#include "base/bitfield.hh"
488229Snate@binkert.org#include "base/misc.hh"
494661Sksewell@umich.edu#include "base/trace.hh"
504661Sksewell@umich.edu
514661Sksewell@umich.edunamespace MipsISA
524661Sksewell@umich.edu{
534661Sksewell@umich.edu
544661Sksewell@umich.edutemplate <class TC>
554661Sksewell@umich.eduinline unsigned
564661Sksewell@umich.edugetVirtProcNum(TC *tc)
574661Sksewell@umich.edu{
586383Sgblack@eecs.umich.edu    TCBindReg tcbind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
596376Sgblack@eecs.umich.edu    return tcbind.curVPE;
604661Sksewell@umich.edu}
614661Sksewell@umich.edu
624661Sksewell@umich.edutemplate <class TC>
634661Sksewell@umich.eduinline unsigned
644661Sksewell@umich.edugetTargetThread(TC *tc)
654661Sksewell@umich.edu{
666383Sgblack@eecs.umich.edu    VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
676376Sgblack@eecs.umich.edu    return vpeCtrl.targTC;
684661Sksewell@umich.edu}
694661Sksewell@umich.edu
704661Sksewell@umich.edutemplate <class TC>
714661Sksewell@umich.eduinline void
724661Sksewell@umich.eduhaltThread(TC *tc)
734661Sksewell@umich.edu{
744661Sksewell@umich.edu    if (tc->status() == TC::Active) {
754661Sksewell@umich.edu        tc->halt();
764661Sksewell@umich.edu
774661Sksewell@umich.edu        // Save last known PC in TCRestart
786378Sgblack@eecs.umich.edu        // @TODO: Needs to check if this is a branch and if so,
796378Sgblack@eecs.umich.edu        // take previous instruction
807720Sgblack@eecs.umich.edu        PCState pc = tc->pcState();
817720Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_TC_RESTART, pc.npc());
824661Sksewell@umich.edu
836378Sgblack@eecs.umich.edu        warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x",
847823Ssteve.reinhardt@amd.com                curTick(), tc->threadId(), tc->getCpuPtr()->name(),
857720Sgblack@eecs.umich.edu                pc.pc(), pc.npc());
864661Sksewell@umich.edu    }
874661Sksewell@umich.edu}
884661Sksewell@umich.edu
894661Sksewell@umich.edutemplate <class TC>
904661Sksewell@umich.eduinline void
914661Sksewell@umich.edurestoreThread(TC *tc)
924661Sksewell@umich.edu{
934661Sksewell@umich.edu    if (tc->status() != TC::Active) {
944661Sksewell@umich.edu        // Restore PC from TCRestart
957720Sgblack@eecs.umich.edu        Addr restartPC = tc->readMiscRegNoEffect(MISCREG_TC_RESTART);
964661Sksewell@umich.edu
974661Sksewell@umich.edu        // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
987720Sgblack@eecs.umich.edu        tc->pcState(restartPC);
999180Sandreas.hansson@arm.com        tc->activate(Cycles(0));
1004661Sksewell@umich.edu
1016378Sgblack@eecs.umich.edu        warn("%i: Restoring thread %i in %s @ PC %x",
1027823Ssteve.reinhardt@amd.com                curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC);
1034661Sksewell@umich.edu    }
1044661Sksewell@umich.edu}
1054661Sksewell@umich.edu
1064661Sksewell@umich.edutemplate <class TC>
1074661Sksewell@umich.eduvoid
1084661Sksewell@umich.eduforkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
1094661Sksewell@umich.edu{
1106383Sgblack@eecs.umich.edu    MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0);
1116376Sgblack@eecs.umich.edu    int num_threads = mvpConf.ptc + 1;
1124661Sksewell@umich.edu
1134661Sksewell@umich.edu    int success = 0;
1146221Snate@binkert.org    for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
1156376Sgblack@eecs.umich.edu        TCBindReg tidTCBind =
1169918Ssteve.reinhardt@amd.com            tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base, tid);
1176383Sgblack@eecs.umich.edu        TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
1184661Sksewell@umich.edu
1196424Snate@binkert.org        if (tidTCBind.curVPE == tcBind.curVPE) {
1204661Sksewell@umich.edu
1216376Sgblack@eecs.umich.edu            TCStatusReg tidTCStatus =
1226383Sgblack@eecs.umich.edu                tc->readRegOtherThread(MISCREG_TC_STATUS +
1239918Ssteve.reinhardt@amd.com                                       Misc_Reg_Base,tid);
1244661Sksewell@umich.edu
1256376Sgblack@eecs.umich.edu            TCHaltReg tidTCHalt =
1269918Ssteve.reinhardt@amd.com                tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,tid);
1274661Sksewell@umich.edu
1286376Sgblack@eecs.umich.edu            if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
1296376Sgblack@eecs.umich.edu                tidTCStatus.a == 0 && success == 0) {
1304661Sksewell@umich.edu
1316383Sgblack@eecs.umich.edu                tc->setRegOtherThread(MISCREG_TC_RESTART +
1329918Ssteve.reinhardt@amd.com                                      Misc_Reg_Base, Rs, tid);
1334661Sksewell@umich.edu                tc->setRegOtherThread(Rd_bits, Rt, tid);
1344661Sksewell@umich.edu
1356383Sgblack@eecs.umich.edu                StatusReg status = tc->readMiscReg(MISCREG_STATUS);
1366383Sgblack@eecs.umich.edu                TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS);
1374661Sksewell@umich.edu
1384661Sksewell@umich.edu                // Set Run-State to Running
1396376Sgblack@eecs.umich.edu                tidTCStatus.rnst = 0;
1404661Sksewell@umich.edu                // Set Delay-Slot to 0
1416376Sgblack@eecs.umich.edu                tidTCStatus.tds = 0;
1424661Sksewell@umich.edu                // Set Dirty TC to 1
1436376Sgblack@eecs.umich.edu                tidTCStatus.dt = 1;
1444661Sksewell@umich.edu                // Set Activated to 1
1456376Sgblack@eecs.umich.edu                tidTCStatus.a = 1;
1464661Sksewell@umich.edu                // Set status to previous thread's status
1476376Sgblack@eecs.umich.edu                tidTCStatus.tksu = status.ksu;
1484661Sksewell@umich.edu                // Set ASID to previous thread's state
1496376Sgblack@eecs.umich.edu                tidTCStatus.asid = tcStatus.asid;
1504661Sksewell@umich.edu
1514661Sksewell@umich.edu                // Write Status Register
1529918Ssteve.reinhardt@amd.com                tc->setRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
1536376Sgblack@eecs.umich.edu                                      tidTCStatus, tid);
1544661Sksewell@umich.edu
1554661Sksewell@umich.edu                // Mark As Successful Fork
1564661Sksewell@umich.edu                success = 1;
1574661Sksewell@umich.edu            }
1584661Sksewell@umich.edu        } else {
1595991Ssteve.reinhardt@amd.com            std::cerr << "Bad VPEs" << std::endl;
1604661Sksewell@umich.edu        }
1614661Sksewell@umich.edu    }
1624661Sksewell@umich.edu
1634661Sksewell@umich.edu    if (success == 0) {
1646383Sgblack@eecs.umich.edu        VPEControlReg vpeControl =
1656383Sgblack@eecs.umich.edu            tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
1666376Sgblack@eecs.umich.edu        vpeControl.excpt = 1;
1676383Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl);
1684661Sksewell@umich.edu        fault = new ThreadFault();
1694661Sksewell@umich.edu    }
1704661Sksewell@umich.edu}
1714661Sksewell@umich.edu
1724661Sksewell@umich.edu
1734661Sksewell@umich.edutemplate <class TC>
1744661Sksewell@umich.eduint
1754661Sksewell@umich.eduyieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
1764661Sksewell@umich.edu{
1774661Sksewell@umich.edu    if (src_reg == 0) {
1786383Sgblack@eecs.umich.edu        MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0);
1796376Sgblack@eecs.umich.edu        ThreadID num_threads = mvpConf0.ptc + 1;
1804661Sksewell@umich.edu
1814661Sksewell@umich.edu        int ok = 0;
1824661Sksewell@umich.edu
1834661Sksewell@umich.edu        // Get Current VPE & TC numbers from calling thread
1846383Sgblack@eecs.umich.edu        TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
1854661Sksewell@umich.edu
1866221Snate@binkert.org        for (ThreadID tid = 0; tid < num_threads; tid++) {
1876376Sgblack@eecs.umich.edu            TCStatusReg tidTCStatus =
1889918Ssteve.reinhardt@amd.com                tc->readRegOtherThread(MISCREG_TC_STATUS + Misc_Reg_Base,
1896383Sgblack@eecs.umich.edu                                       tid);
1906376Sgblack@eecs.umich.edu            TCHaltReg tidTCHalt =
1919918Ssteve.reinhardt@amd.com                tc->readRegOtherThread(MISCREG_TC_HALT + Misc_Reg_Base,
1926383Sgblack@eecs.umich.edu                                       tid);
1936376Sgblack@eecs.umich.edu            TCBindReg tidTCBind =
1949918Ssteve.reinhardt@amd.com                tc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base,
1956383Sgblack@eecs.umich.edu                                       tid);
1964661Sksewell@umich.edu
1976376Sgblack@eecs.umich.edu            if (tidTCBind.curVPE == tcBind.curVPE &&
1986376Sgblack@eecs.umich.edu                tidTCBind.curTC == tcBind.curTC &&
1996376Sgblack@eecs.umich.edu                tidTCStatus.da == 1 &&
2006376Sgblack@eecs.umich.edu                tidTCHalt.h == 0    &&
2016376Sgblack@eecs.umich.edu                tidTCStatus.a == 1) {
2024661Sksewell@umich.edu                ok = 1;
2034661Sksewell@umich.edu            }
2044661Sksewell@umich.edu        }
2054661Sksewell@umich.edu
2064661Sksewell@umich.edu        if (ok == 1) {
2076383Sgblack@eecs.umich.edu            TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
2086376Sgblack@eecs.umich.edu            tcStatus.a = 0;
2096383Sgblack@eecs.umich.edu            tc->setMiscReg(MISCREG_TC_STATUS, tcStatus);
2106376Sgblack@eecs.umich.edu            warn("%i: Deactivating Hardware Thread Context #%i",
2117823Ssteve.reinhardt@amd.com                    curTick(), tc->threadId());
2124661Sksewell@umich.edu        }
2134661Sksewell@umich.edu    } else if (src_reg > 0) {
2145561Snate@binkert.org        if (src_reg && !yield_mask != 0) {
2156383Sgblack@eecs.umich.edu            VPEControlReg vpeControl = tc->readMiscReg(MISCREG_VPE_CONTROL);
2166376Sgblack@eecs.umich.edu            vpeControl.excpt = 2;
2176383Sgblack@eecs.umich.edu            tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl);
2184661Sksewell@umich.edu            fault = new ThreadFault();
2194661Sksewell@umich.edu        } else {
2204661Sksewell@umich.edu        }
2214661Sksewell@umich.edu    } else if (src_reg != -2) {
2226383Sgblack@eecs.umich.edu        TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
2236383Sgblack@eecs.umich.edu        VPEControlReg vpeControl =
2246383Sgblack@eecs.umich.edu            tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
2254661Sksewell@umich.edu
2266376Sgblack@eecs.umich.edu        if (vpeControl.ysi == 1 && tcStatus.dt == 1 ) {
2276376Sgblack@eecs.umich.edu            vpeControl.excpt = 4;
2284661Sksewell@umich.edu            fault = new ThreadFault();
2294661Sksewell@umich.edu        } else {
2304661Sksewell@umich.edu        }
2314661Sksewell@umich.edu    }
2324661Sksewell@umich.edu
2334661Sksewell@umich.edu    return src_reg & yield_mask;
2344661Sksewell@umich.edu}
2354661Sksewell@umich.edu
2364661Sksewell@umich.edu
2374661Sksewell@umich.edu// TC will usually be a object derived from ThreadContext
2384661Sksewell@umich.edu// (src/cpu/thread_context.hh)
2394661Sksewell@umich.edutemplate <class TC>
2404661Sksewell@umich.eduinline void
2414661Sksewell@umich.eduupdateStatusView(TC *tc)
2424661Sksewell@umich.edu{
2434661Sksewell@umich.edu    // TCStatus' register view must be the same as
2444661Sksewell@umich.edu    // Status register view for CU, MX, KSU bits
2456383Sgblack@eecs.umich.edu    TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
2466383Sgblack@eecs.umich.edu    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
2474661Sksewell@umich.edu
2486376Sgblack@eecs.umich.edu    status.cu = tcStatus.tcu;
2496376Sgblack@eecs.umich.edu    status.mx = tcStatus.tmx;
2506376Sgblack@eecs.umich.edu    status.ksu = tcStatus.tksu;
2514661Sksewell@umich.edu
2526383Sgblack@eecs.umich.edu    tc->setMiscRegNoEffect(MISCREG_STATUS, status);
2534661Sksewell@umich.edu}
2544661Sksewell@umich.edu
2554661Sksewell@umich.edu// TC will usually be a object derived from ThreadContext
2564661Sksewell@umich.edu// (src/cpu/thread_context.hh)
2574661Sksewell@umich.edutemplate <class TC>
2584661Sksewell@umich.eduinline void
2594661Sksewell@umich.eduupdateTCStatusView(TC *tc)
2604661Sksewell@umich.edu{
2614661Sksewell@umich.edu    // TCStatus' register view must be the same as
2624661Sksewell@umich.edu    // Status register view for CU, MX, KSU bits
2636383Sgblack@eecs.umich.edu    TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
2646383Sgblack@eecs.umich.edu    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
2654661Sksewell@umich.edu
2666376Sgblack@eecs.umich.edu    tcStatus.tcu = status.cu;
2676376Sgblack@eecs.umich.edu    tcStatus.tmx = status.mx;
2686376Sgblack@eecs.umich.edu    tcStatus.tksu = status.ksu;
2694661Sksewell@umich.edu
2706383Sgblack@eecs.umich.edu    tc->setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
2714661Sksewell@umich.edu}
2724661Sksewell@umich.edu
2734661Sksewell@umich.edu} // namespace MipsISA
2744661Sksewell@umich.edu
2754661Sksewell@umich.edu
2764661Sksewell@umich.edu#endif
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