mt.hh revision 5715
14661Sksewell@umich.edu/*
25268Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc.
35268Sksewell@umich.edu * All rights reserved.
44661Sksewell@umich.edu *
55268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without
65268Sksewell@umich.edu * modification, are permitted provided that the following conditions are
75268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright
85268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer;
95268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright
105268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the
115268Sksewell@umich.edu * documentation and/or other materials provided with the distribution;
125268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its
135268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from
145268Sksewell@umich.edu * this software without specific prior written permission.
154661Sksewell@umich.edu *
165268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
175268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
185268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
195268Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
205268Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
215268Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
225268Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
235268Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
245268Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
255268Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
265268Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
275222Sksewell@umich.edu *
285254Sksewell@umich.edu * Authors: Korey Sewell
294661Sksewell@umich.edu */
304661Sksewell@umich.edu
314661Sksewell@umich.edu#ifndef __ARCH_MIPS_MT_HH__
324661Sksewell@umich.edu#define __ARCH_MIPS_MT_HH__
334661Sksewell@umich.edu
344661Sksewell@umich.edu/**
354661Sksewell@umich.edu * @file
364661Sksewell@umich.edu *
374661Sksewell@umich.edu * ISA-specific helper functions for multithreaded execution.
384661Sksewell@umich.edu */
394661Sksewell@umich.edu
404661Sksewell@umich.edu#include "arch/isa_traits.hh"
414661Sksewell@umich.edu#include "arch/mips/faults.hh"
424661Sksewell@umich.edu#include "arch/mips/mt_constants.hh"
434661Sksewell@umich.edu#include "base/bitfield.hh"
444661Sksewell@umich.edu#include "base/trace.hh"
454661Sksewell@umich.edu#include "base/misc.hh"
464661Sksewell@umich.edu
474661Sksewell@umich.edu#include <iostream>
484661Sksewell@umich.eduusing namespace std;
494661Sksewell@umich.edu
504661Sksewell@umich.edunamespace MipsISA
514661Sksewell@umich.edu{
524661Sksewell@umich.edu
534661Sksewell@umich.edu
544661Sksewell@umich.edutemplate <class TC>
554661Sksewell@umich.eduinline unsigned
564661Sksewell@umich.edugetVirtProcNum(TC *tc)
574661Sksewell@umich.edu{
584661Sksewell@umich.edu    MiscReg tcbind = tc->readMiscRegNoEffect(TCBind);
594661Sksewell@umich.edu    return bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
604661Sksewell@umich.edu}
614661Sksewell@umich.edu
624661Sksewell@umich.edutemplate <class TC>
634661Sksewell@umich.eduinline unsigned
644661Sksewell@umich.edugetTargetThread(TC *tc)
654661Sksewell@umich.edu{
664661Sksewell@umich.edu    MiscReg vpec_ctrl = tc->readMiscRegNoEffect(VPEControl);
674661Sksewell@umich.edu    return bits(vpec_ctrl, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO);
684661Sksewell@umich.edu}
694661Sksewell@umich.edu
704661Sksewell@umich.edutemplate <class TC>
714661Sksewell@umich.eduinline void
724661Sksewell@umich.eduhaltThread(TC *tc)
734661Sksewell@umich.edu{
744661Sksewell@umich.edu    if (tc->status() == TC::Active) {
754661Sksewell@umich.edu        tc->halt();
764661Sksewell@umich.edu
774661Sksewell@umich.edu        // Save last known PC in TCRestart
784661Sksewell@umich.edu        // @TODO: Needs to check if this is a branch and if so, take previous instruction
794661Sksewell@umich.edu        tc->setMiscReg(TCRestart, tc->readNextPC());
804661Sksewell@umich.edu
815715Shsul@eecs.umich.edu        warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
824661Sksewell@umich.edu             tc->readPC(), tc->readNextPC());
834661Sksewell@umich.edu    }
844661Sksewell@umich.edu}
854661Sksewell@umich.edu
864661Sksewell@umich.edutemplate <class TC>
874661Sksewell@umich.eduinline void
884661Sksewell@umich.edurestoreThread(TC *tc)
894661Sksewell@umich.edu{
904661Sksewell@umich.edu    if (tc->status() != TC::Active) {
914661Sksewell@umich.edu        // Restore PC from TCRestart
924661Sksewell@umich.edu        IntReg pc = tc->readMiscRegNoEffect(TCRestart);
934661Sksewell@umich.edu
944661Sksewell@umich.edu        // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
954661Sksewell@umich.edu        // tc->setPCEvent(pc, pc + 4, pc + 8);
964661Sksewell@umich.edu        tc->setPC(pc);
974661Sksewell@umich.edu        tc->setNextPC(pc + 4);
984661Sksewell@umich.edu        tc->setNextNPC(pc + 8);
994661Sksewell@umich.edu        tc->activate(0);
1004661Sksewell@umich.edu
1015715Shsul@eecs.umich.edu        warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->threadId(), tc->getCpuPtr()->name(),
1024661Sksewell@umich.edu             tc->readPC());
1034661Sksewell@umich.edu    }
1044661Sksewell@umich.edu}
1054661Sksewell@umich.edu
1064661Sksewell@umich.edutemplate <class TC>
1074661Sksewell@umich.eduvoid
1084661Sksewell@umich.eduforkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
1094661Sksewell@umich.edu{
1104661Sksewell@umich.edu    int num_threads = bits(tc->readMiscRegNoEffect(MVPConf0), MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
1114661Sksewell@umich.edu
1124661Sksewell@umich.edu    int success = 0;
1134661Sksewell@umich.edu    for (int tid = 0; tid < num_threads && success == 0; tid++) {
1144661Sksewell@umich.edu        unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
1154661Sksewell@umich.edu                                                     tid);
1164661Sksewell@umich.edu        unsigned tc_bind = tc->readMiscRegNoEffect(MipsISA::TCBind);
1174661Sksewell@umich.edu
1184661Sksewell@umich.edu        if (bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) ==
1194661Sksewell@umich.edu            bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) {
1204661Sksewell@umich.edu
1214661Sksewell@umich.edu            unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
1224661Sksewell@umich.edu                                                           tid);
1234661Sksewell@umich.edu
1244661Sksewell@umich.edu            unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
1254661Sksewell@umich.edu                                                         tid);
1264661Sksewell@umich.edu
1274661Sksewell@umich.edu            if (bits(tid_TCStatus, TCS_DA) == 1 &&
1284661Sksewell@umich.edu                bits(tid_TCHalt, TCH_H) == 0    &&
1294661Sksewell@umich.edu                bits(tid_TCStatus, TCS_A) == 0  &&
1304661Sksewell@umich.edu                success == 0) {
1314661Sksewell@umich.edu
1324661Sksewell@umich.edu                tc->setRegOtherThread(MipsISA::TCRestart + Ctrl_Base_DepTag, Rs, tid);
1334661Sksewell@umich.edu
1344661Sksewell@umich.edu                tc->setRegOtherThread(Rd_bits, Rt, tid);
1354661Sksewell@umich.edu
1364661Sksewell@umich.edu                unsigned status_ksu = bits(tc->readMiscReg(MipsISA::Status),
1374661Sksewell@umich.edu                                           S_KSU_HI, S_KSU_LO);
1384661Sksewell@umich.edu                unsigned tc_status_asid = bits(tc->readMiscReg(MipsISA::TCStatus),
1394661Sksewell@umich.edu                                          TCS_ASID_HI, TCS_ASID_LO);
1404661Sksewell@umich.edu
1414661Sksewell@umich.edu                // Set Run-State to Running
1424661Sksewell@umich.edu                replaceBits(tid_TCStatus, TCSTATUS_RNST_HI, TCSTATUS_RNST_LO, 0);
1434661Sksewell@umich.edu
1444661Sksewell@umich.edu                // Set Delay-Slot to 0
1454661Sksewell@umich.edu                replaceBits(tid_TCStatus, TCSTATUS_TDS, 0);
1464661Sksewell@umich.edu
1474661Sksewell@umich.edu                // Set Dirty TC to 1
1484661Sksewell@umich.edu                replaceBits(tid_TCStatus, TCSTATUS_DT, 1);
1494661Sksewell@umich.edu
1504661Sksewell@umich.edu                // Set Activated to 1
1514661Sksewell@umich.edu                replaceBits(tid_TCStatus, TCSTATUS_A, 1);
1524661Sksewell@umich.edu
1534661Sksewell@umich.edu                // Set status to previous thread's status
1544661Sksewell@umich.edu                replaceBits(tid_TCStatus, TCSTATUS_TKSU_HI, TCSTATUS_TKSU_LO, status_ksu);
1554661Sksewell@umich.edu
1564661Sksewell@umich.edu                // Set ASID to previous thread's state
1574661Sksewell@umich.edu                replaceBits(tid_TCStatus, TCSTATUS_ASID_HI, TCSTATUS_ASID_LO, tc_status_asid);
1584661Sksewell@umich.edu
1594661Sksewell@umich.edu                // Write Status Register
1604661Sksewell@umich.edu                tc->setRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
1614661Sksewell@umich.edu                                      tid_TCStatus, tid);
1624661Sksewell@umich.edu
1634661Sksewell@umich.edu                // Mark As Successful Fork
1644661Sksewell@umich.edu                success = 1;
1654661Sksewell@umich.edu            }
1664661Sksewell@umich.edu        } else {
1674661Sksewell@umich.edu            std::cerr << "Bad VPEs" << endl;
1684661Sksewell@umich.edu        }
1694661Sksewell@umich.edu    }
1704661Sksewell@umich.edu
1714661Sksewell@umich.edu    if (success == 0) {
1724661Sksewell@umich.edu        unsigned vpe_control = tc->readMiscRegNoEffect(MipsISA::VPEControl);
1734661Sksewell@umich.edu        tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 1));
1744661Sksewell@umich.edu        fault = new ThreadFault();
1754661Sksewell@umich.edu    }
1764661Sksewell@umich.edu}
1774661Sksewell@umich.edu
1784661Sksewell@umich.edu
1794661Sksewell@umich.edutemplate <class TC>
1804661Sksewell@umich.eduint
1814661Sksewell@umich.eduyieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
1824661Sksewell@umich.edu{
1834661Sksewell@umich.edu    if (src_reg == 0) {
1844661Sksewell@umich.edu        unsigned mvpconf0 = tc->readMiscRegNoEffect(MVPConf0);
1854661Sksewell@umich.edu        int num_threads = bits(mvpconf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
1864661Sksewell@umich.edu
1874661Sksewell@umich.edu        int ok = 0;
1884661Sksewell@umich.edu
1894661Sksewell@umich.edu        // Get Current VPE & TC numbers from calling thread
1904661Sksewell@umich.edu        unsigned tcbind = tc->readMiscRegNoEffect(TCBind);
1914661Sksewell@umich.edu        unsigned cur_vpe = bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
1924661Sksewell@umich.edu        unsigned cur_tc = bits(tcbind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
1934661Sksewell@umich.edu
1944661Sksewell@umich.edu        for (int tid = 0; tid < num_threads; tid++) {
1954661Sksewell@umich.edu            unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
1964661Sksewell@umich.edu                                                           tid);
1974661Sksewell@umich.edu            unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
1984661Sksewell@umich.edu                                                         tid);
1994661Sksewell@umich.edu            unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
2004661Sksewell@umich.edu                                                         tid);
2014661Sksewell@umich.edu
2024661Sksewell@umich.edu            unsigned tid_vpe = bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
2034661Sksewell@umich.edu            unsigned tid_tc = bits(tid_TCBind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
2044661Sksewell@umich.edu            unsigned tid_tcstatus_da = bits(tid_TCStatus, TCS_DA);
2054661Sksewell@umich.edu            unsigned tid_tcstatus_a = bits(tid_TCStatus, TCS_A);
2064661Sksewell@umich.edu            unsigned tid_tchalt_h = bits(tid_TCHalt, TCH_H);
2074661Sksewell@umich.edu
2084661Sksewell@umich.edu            if (tid_vpe == cur_vpe &&
2094661Sksewell@umich.edu                tid_tc == cur_tc &&
2104661Sksewell@umich.edu                tid_tcstatus_da == 1 &&
2114661Sksewell@umich.edu                tid_tchalt_h == 0    &&
2124661Sksewell@umich.edu                tid_tcstatus_a == 1) {
2134661Sksewell@umich.edu                ok = 1;
2144661Sksewell@umich.edu            }
2154661Sksewell@umich.edu        }
2164661Sksewell@umich.edu
2174661Sksewell@umich.edu        if (ok == 1) {
2184661Sksewell@umich.edu            unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
2194661Sksewell@umich.edu            tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0));
2205715Shsul@eecs.umich.edu            warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId());
2214661Sksewell@umich.edu        }
2224661Sksewell@umich.edu    } else if (src_reg > 0) {
2235561Snate@binkert.org        if (src_reg && !yield_mask != 0) {
2244661Sksewell@umich.edu            unsigned vpe_control = tc->readMiscReg(VPEControl);
2254661Sksewell@umich.edu            tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 2));
2264661Sksewell@umich.edu            fault = new ThreadFault();
2274661Sksewell@umich.edu        } else {
2284661Sksewell@umich.edu            //tc->setThreadRescheduleCondition(src_reg & yield_mask);
2294661Sksewell@umich.edu        }
2304661Sksewell@umich.edu    } else if (src_reg != -2) {
2314661Sksewell@umich.edu        unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
2324661Sksewell@umich.edu        unsigned vpe_control = tc->readMiscRegNoEffect(VPEControl);
2334661Sksewell@umich.edu        unsigned tcstatus_dt = bits(tcstatus, TCS_DT);
2344661Sksewell@umich.edu        unsigned vpe_control_ysi = bits(vpe_control, VPEC_YSI);
2354661Sksewell@umich.edu
2364661Sksewell@umich.edu        if (vpe_control_ysi == 1 && tcstatus_dt == 1 ) {
2374661Sksewell@umich.edu            tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 4));
2384661Sksewell@umich.edu            fault = new ThreadFault();
2394661Sksewell@umich.edu        } else {
2404661Sksewell@umich.edu            //tc->ScheduleOtherThreads();
2415715Shsul@eecs.umich.edu            //std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other Threads.\n" << std::endl;
2424661Sksewell@umich.edu            //tc->suspend();
2434661Sksewell@umich.edu            // Save last known PC in TCRestart
2444661Sksewell@umich.edu            // @TODO: Needs to check if this is a branch and if so, take previous instruction
2454661Sksewell@umich.edu            //tc->setMiscRegWithEffect(TCRestart, tc->readNextPC());
2464661Sksewell@umich.edu        }
2474661Sksewell@umich.edu    }
2484661Sksewell@umich.edu
2494661Sksewell@umich.edu    return src_reg & yield_mask;
2504661Sksewell@umich.edu}
2514661Sksewell@umich.edu
2524661Sksewell@umich.edu
2534661Sksewell@umich.edu// TC will usually be a object derived from ThreadContext
2544661Sksewell@umich.edu// (src/cpu/thread_context.hh)
2554661Sksewell@umich.edutemplate <class TC>
2564661Sksewell@umich.eduinline void
2574661Sksewell@umich.eduupdateStatusView(TC *tc)
2584661Sksewell@umich.edu{
2594661Sksewell@umich.edu    // TCStatus' register view must be the same as
2604661Sksewell@umich.edu    // Status register view for CU, MX, KSU bits
2614661Sksewell@umich.edu    MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
2624661Sksewell@umich.edu    MiscReg status = tc->readMiscRegNoEffect(Status);
2634661Sksewell@umich.edu
2644661Sksewell@umich.edu    unsigned cu_bits = bits(tc_status, TCS_TCU_HI, TCS_TCU_LO);
2654661Sksewell@umich.edu    replaceBits(status, S_CU_HI, S_CU_LO, cu_bits);
2664661Sksewell@umich.edu
2674661Sksewell@umich.edu    unsigned mx_bits = bits(tc_status, TCS_TMX);
2684661Sksewell@umich.edu    replaceBits(status, S_MX, S_MX, mx_bits);
2694661Sksewell@umich.edu
2704661Sksewell@umich.edu    unsigned ksu_bits = bits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO);
2714661Sksewell@umich.edu    replaceBits(status, S_KSU_HI, S_KSU_LO, ksu_bits);
2724661Sksewell@umich.edu
2734661Sksewell@umich.edu    tc->setMiscRegNoEffect(Status, status);
2744661Sksewell@umich.edu}
2754661Sksewell@umich.edu
2764661Sksewell@umich.edu// TC will usually be a object derived from ThreadContext
2774661Sksewell@umich.edu// (src/cpu/thread_context.hh)
2784661Sksewell@umich.edutemplate <class TC>
2794661Sksewell@umich.eduinline void
2804661Sksewell@umich.eduupdateTCStatusView(TC *tc)
2814661Sksewell@umich.edu{
2824661Sksewell@umich.edu    // TCStatus' register view must be the same as
2834661Sksewell@umich.edu    // Status register view for CU, MX, KSU bits
2844661Sksewell@umich.edu    MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
2854661Sksewell@umich.edu    MiscReg status = tc->readMiscRegNoEffect(Status);
2864661Sksewell@umich.edu
2874661Sksewell@umich.edu    unsigned cu_bits = bits(status, S_CU_HI, S_CU_LO);
2884661Sksewell@umich.edu    replaceBits(tc_status, TCS_TCU_HI, TCS_TCU_LO, cu_bits);
2894661Sksewell@umich.edu
2904661Sksewell@umich.edu    unsigned mx_bits = bits(status, S_MX, S_MX);
2914661Sksewell@umich.edu    replaceBits(tc_status, TCS_TMX, mx_bits);
2924661Sksewell@umich.edu
2934661Sksewell@umich.edu    unsigned ksu_bits = bits(status, S_KSU_HI, S_KSU_LO);
2944661Sksewell@umich.edu    replaceBits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO, ksu_bits);
2954661Sksewell@umich.edu
2964661Sksewell@umich.edu    tc->setMiscRegNoEffect(TCStatus, tc_status);
2974661Sksewell@umich.edu}
2984661Sksewell@umich.edu
2994661Sksewell@umich.edu} // namespace MipsISA
3004661Sksewell@umich.edu
3014661Sksewell@umich.edu
3024661Sksewell@umich.edu#endif
303