mmapped_ipr.hh revision 5222
12SN/A/* 21762SN/A * Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved 32SN/A * 42SN/A * This software is part of the M5 simulator. 52SN/A * 62SN/A * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 72SN/A * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 82SN/A * TO THESE TERMS AND CONDITIONS. 92SN/A * 102SN/A * Permission is granted to use, copy, create derivative works and 112SN/A * distribute this software and such derivative works for any purpose, 122SN/A * so long as (1) the copyright notice above, this grant of permission, 132SN/A * and the disclaimer below appear in all copies and derivative works 142SN/A * made, (2) the copyright notice above is augmented as appropriate to 152SN/A * reflect the addition of any new copyrightable work in a derivative 162SN/A * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3) 172SN/A * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any 182SN/A * advertising or publicity pertaining to the use or distribution of 192SN/A * this software without specific, written prior authorization. 202SN/A * 212SN/A * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 222SN/A * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 232SN/A * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 242SN/A * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 252SN/A * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 262SN/A * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 272665Ssaidi@eecs.umich.edu * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 282665Ssaidi@eecs.umich.edu * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 292665Ssaidi@eecs.umich.edu * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 302665Ssaidi@eecs.umich.edu * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 312SN/A * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 322SN/A * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 332SN/A * 342SN/A * Authors: Jaidev Patwardhan 352SN/A * 362984Sgblack@eecs.umich.edu */ 372171SN/A 382984Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_MMAPED_IPR_HH__ 39146SN/A#define __ARCH_MIPS_MMAPED_IPR_HH__ 40146SN/A 41146SN/A/** 421858SN/A * @file 432680Sktlim@umich.edu * 444762Snate@binkert.org * ISA-specific helper functions for memory mapped IPR accesses. 454762Snate@binkert.org */ 462SN/A 472SN/A#include "base/misc.hh" 481147SN/A#include "mem/packet.hh" 492SN/A 504088Sbinkertn@umich.educlass ThreadContext; 513838Shsul@eecs.umich.edu 523838Shsul@eecs.umich.edunamespace MipsISA 533838Shsul@eecs.umich.edu{ 543838Shsul@eecs.umich.eduinline Tick 55860SN/AhandleIprRead(ThreadContext *xc, Packet *pkt) 563838Shsul@eecs.umich.edu{ 573838Shsul@eecs.umich.edu panic("No implementation for handleIprRead in MIPS\n"); 58860SN/A} 59860SN/A 601147SN/Ainline Tick 611147SN/AhandleIprWrite(ThreadContext *xc, Packet *pkt) 623838Shsul@eecs.umich.edu{ 633838Shsul@eecs.umich.edu panic("No implementation for handleIprWrite in MIPS\n"); 643838Shsul@eecs.umich.edu} 655004Sgblack@eecs.umich.edu 665004Sgblack@eecs.umich.edu 674957Sacolyte@umich.edu} // namespace MipsISA 683838Shsul@eecs.umich.edu 692SN/A#endif 703838Shsul@eecs.umich.edu