locked_mem.hh revision 5222:bb733a878f85 
1/*
2 * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
3 *
4 * This software is part of the M5 simulator.
5 *
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8 * TO THESE TERMS AND CONDITIONS.
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11 * distribute this software and such derivative works for any purpose,
12 * so long as (1) the copyright notice above, this grant of permission,
13 * and the disclaimer below appear in all copies and derivative works
14 * made, (2) the copyright notice above is augmented as appropriate to
15 * reflect the addition of any new copyrightable work in a derivative
16 * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
17 * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
18 * advertising or publicity pertaining to the use or distribution of
19 * this software without specific, written prior authorization.
20 *
21 * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
22 * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
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24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
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28 * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
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33 *
34 * Authors: Steven K. Reinhardt
35 */
36
37#ifndef __ARCH_MIPS_LOCKED_MEM_HH__
38#define __ARCH_MIPS_LOCKED_MEM_HH__
39
40/**
41 * @file
42 *
43 * ISA-specific helper functions for locked memory accesses.
44 */
45
46#include "arch/isa_traits.hh"
47#include "base/misc.hh"
48#include "base/trace.hh"
49#include "mem/request.hh"
50
51
52namespace MipsISA
53{
54template <class XC>
55inline void
56handleLockedRead(XC *xc, Request *req)
57{
58    unsigned tid = req->getThreadNum();
59    xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf, tid);
60    xc->setMiscRegNoEffect(LLFlag, true, tid);
61    DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
62            tid, req->getPaddr() & ~0xf);
63}
64
65
66template <class XC>
67inline bool
68handleLockedWrite(XC *xc, Request *req)
69{
70    unsigned tid = req->getThreadNum();
71
72    if (req->isUncacheable()) {
73        // Funky Turbolaser mailbox access...don't update
74        // result register (see stq_c in decoder.isa)
75        req->setExtraData(2);
76    } else {
77        // standard store conditional
78        bool lock_flag = xc->readMiscRegNoEffect(LLFlag, tid);
79        Addr lock_addr = xc->readMiscRegNoEffect(LLAddr, tid);
80
81        if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
82            // Lock flag not set or addr mismatch in CPU;
83            // don't even bother sending to memory system
84            req->setExtraData(0);
85            xc->setMiscRegNoEffect(LLFlag, false, tid);
86
87            // the rest of this code is not architectural;
88            // it's just a debugging aid to help detect
89            // livelock by warning on long sequences of failed
90            // store conditionals
91            int stCondFailures = xc->readStCondFailures();
92            stCondFailures++;
93            xc->setStCondFailures(stCondFailures);
94            if (stCondFailures % 10 == 0) {
95                warn("%i: cpu %d: %d consecutive "
96                     "store conditional failures\n",
97                     curTick, xc->readCpuId(), stCondFailures);
98            }
99
100            if (stCondFailures == 5000) {
101                panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n");
102            }
103
104            if (!lock_flag){
105                DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
106                        tid);
107            } else if ((req->getPaddr() & ~0xf) != lock_addr) {
108                DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
109                        tid);
110            }
111            // store conditional failed already, so don't issue it to mem
112            return false;
113        }
114    }
115
116    return true;
117}
118
119
120} // namespace MipsISA
121
122#endif
123