locked_mem.hh revision 4661:44458219add1 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __ARCH_MIPS_LOCKED_MEM_HH__
32#define __ARCH_MIPS_LOCKED_MEM_HH__
33
34/**
35 * @file
36 *
37 * ISA-specific helper functions for locked memory accesses.
38 */
39
40#include "arch/isa_traits.hh"
41#include "base/misc.hh"
42#include "base/trace.hh"
43#include "mem/request.hh"
44
45
46namespace MipsISA
47{
48template <class XC>
49inline void
50handleLockedRead(XC *xc, Request *req)
51{
52    unsigned tid = req->getThreadNum();
53    xc->setMiscReg(LLAddr, req->getPaddr() & ~0xf, tid);
54    xc->setMiscReg(LLFlag, true, tid);
55    DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n",
56            tid, req->getPaddr() & ~0xf);
57}
58
59
60template <class XC>
61inline bool
62handleLockedWrite(XC *xc, Request *req)
63{
64    unsigned tid = req->getThreadNum();
65
66    if (req->isUncacheable()) {
67        // Funky Turbolaser mailbox access...don't update
68        // result register (see stq_c in decoder.isa)
69        req->setExtraData(2);
70    } else {
71        // standard store conditional
72        bool lock_flag = xc->readMiscReg(LLFlag, tid);
73        Addr lock_addr = xc->readMiscReg(LLAddr, tid);
74
75        if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
76            // Lock flag not set or addr mismatch in CPU;
77            // don't even bother sending to memory system
78            req->setExtraData(0);
79            xc->setMiscReg(LLFlag, false, tid);
80
81            // the rest of this code is not architectural;
82            // it's just a debugging aid to help detect
83            // livelock by warning on long sequences of failed
84            // store conditionals
85            int stCondFailures = xc->readStCondFailures();
86            stCondFailures++;
87            xc->setStCondFailures(stCondFailures);
88            if (stCondFailures % 10 == 0) {
89                warn("%i: cpu %d: %d consecutive "
90                     "store conditional failures\n",
91                     curTick, xc->readCpuId(), stCondFailures);
92            }
93
94            if (stCondFailures == 5000) {
95                panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n");
96            }
97
98            if (!lock_flag){
99                DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n",
100                        tid);
101            } else if ((req->getPaddr() & ~0xf) != lock_addr) {
102                DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n",
103                        tid);
104            }
105            // store conditional failed already, so don't issue it to mem
106            return false;
107        }
108    }
109
110    return true;
111}
112
113
114} // namespace MipsISA
115
116#endif
117