locked_mem.hh revision 6425
12135SN/A/* 22135SN/A * Copyright (c) 2006-2007 The Regents of The University of Michigan 32754Sksewell@umich.edu * All rights reserved. 42706Sksewell@umich.edu * 52706Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 62706Sksewell@umich.edu * modification, are permitted provided that the following conditions are 72706Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 82706Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 92706Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 102706Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 112706Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 122706Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 132706Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 142706Sksewell@umich.edu * this software without specific prior written permission. 152706Sksewell@umich.edu * 162706Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172706Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182706Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192706Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202706Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212706Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222706Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232706Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242706Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252706Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262706Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272706Sksewell@umich.edu * 282706Sksewell@umich.edu * Authors: Steve Reinhardt 292706Sksewell@umich.edu */ 302706Sksewell@umich.edu 312038SN/A#ifndef __ARCH_MIPS_LOCKED_MEM_HH__ 322038SN/A#define __ARCH_MIPS_LOCKED_MEM_HH__ 332038SN/A 342038SN/A/** 352038SN/A * @file 362038SN/A * 372038SN/A * ISA-specific helper functions for locked memory accesses. 382135SN/A */ 392038SN/A 402038SN/A#include "arch/registers.hh" 412038SN/A#include "base/misc.hh" 422038SN/A#include "base/trace.hh" 432038SN/A#include "mem/request.hh" 442038SN/A 452038SN/A 462038SN/Anamespace MipsISA 472038SN/A{ 482038SN/A 492686Sksewell@umich.edutemplate <class XC> 502686Sksewell@umich.eduinline void 512686Sksewell@umich.eduhandleLockedRead(XC *xc, Request *req) 522686Sksewell@umich.edu{ 532686Sksewell@umich.edu xc->setMiscRegNoEffect(MISCREG_LLADDR, req->getPaddr() & ~0xf); 542686Sksewell@umich.edu xc->setMiscRegNoEffect(MISCREG_LLFLAG, true); 552686Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link" 562686Sksewell@umich.edu " Address set to %x.\n", 572686Sksewell@umich.edu req->threadId(), req->getPaddr() & ~0xf); 582686Sksewell@umich.edu} 592686Sksewell@umich.edu 602686Sksewell@umich.edutemplate <class XC> 612686Sksewell@umich.eduinline bool 622686Sksewell@umich.eduhandleLockedWrite(XC *xc, Request *req) 632038SN/A{ 642038SN/A if (req->isUncacheable()) { 652038SN/A // Funky Turbolaser mailbox access...don't update 662038SN/A // result register (see stq_c in decoder.isa) 672686Sksewell@umich.edu req->setExtraData(2); 682038SN/A } else { 692686Sksewell@umich.edu // standard store conditional 702686Sksewell@umich.edu bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LLFLAG); 712686Sksewell@umich.edu Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LLADDR); 722686Sksewell@umich.edu 732686Sksewell@umich.edu if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 742686Sksewell@umich.edu // Lock flag not set or addr mismatch in CPU; 752686Sksewell@umich.edu // don't even bother sending to memory system 762686Sksewell@umich.edu req->setExtraData(0); 772686Sksewell@umich.edu xc->setMiscRegNoEffect(MISCREG_LLFLAG, false); 782686Sksewell@umich.edu 792686Sksewell@umich.edu // the rest of this code is not architectural; 802686Sksewell@umich.edu // it's just a debugging aid to help detect 812686Sksewell@umich.edu // livelock by warning on long sequences of failed 822686Sksewell@umich.edu // store conditionals 832686Sksewell@umich.edu int stCondFailures = xc->readStCondFailures(); 842686Sksewell@umich.edu stCondFailures++; 852686Sksewell@umich.edu xc->setStCondFailures(stCondFailures); 862038SN/A if (stCondFailures % 100000 == 0) { 872038SN/A warn("%i: context %d: %d consecutive " 882038SN/A "store conditional failures\n", 892686Sksewell@umich.edu curTick, xc->contextId(), stCondFailures); 904661Sksewell@umich.edu } 914661Sksewell@umich.edu 924661Sksewell@umich.edu if (!lock_flag){ 934661Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, " 944661Sksewell@umich.edu "Store Conditional Failed.\n", 954661Sksewell@umich.edu req->threadId()); 962038SN/A } else if ((req->getPaddr() & ~0xf) != lock_addr) { 972686Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, " 982686Sksewell@umich.edu "Store Conditional Failed.\n", 992686Sksewell@umich.edu req->threadId()); 1002686Sksewell@umich.edu } 1012686Sksewell@umich.edu // store conditional failed already, so don't issue it to mem 1022686Sksewell@umich.edu return false; 1032686Sksewell@umich.edu } 1042686Sksewell@umich.edu } 1052686Sksewell@umich.edu 1062686Sksewell@umich.edu return true; 1072686Sksewell@umich.edu} 1083735Sstever@eecs.umich.edu 1092686Sksewell@umich.edu} // namespace MipsISA 1102686Sksewell@umich.edu 1112686Sksewell@umich.edu#endif 1122686Sksewell@umich.edu