locked_mem.hh revision 6329
13170Sstever@eecs.umich.edu/* 25254Sksewell@umich.edu * Copyright (c) 2006-2007 The Regents of The University of Michigan 35254Sksewell@umich.edu * All rights reserved. 43170Sstever@eecs.umich.edu * 55254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 153170Sstever@eecs.umich.edu * 165254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273170Sstever@eecs.umich.edu * 285254Sksewell@umich.edu * Authors: Steve Reinhardt 293170Sstever@eecs.umich.edu */ 303170Sstever@eecs.umich.edu 313170Sstever@eecs.umich.edu#ifndef __ARCH_MIPS_LOCKED_MEM_HH__ 323170Sstever@eecs.umich.edu#define __ARCH_MIPS_LOCKED_MEM_HH__ 333170Sstever@eecs.umich.edu 343170Sstever@eecs.umich.edu/** 353170Sstever@eecs.umich.edu * @file 363170Sstever@eecs.umich.edu * 373170Sstever@eecs.umich.edu * ISA-specific helper functions for locked memory accesses. 383170Sstever@eecs.umich.edu */ 393170Sstever@eecs.umich.edu 406329Sgblack@eecs.umich.edu#include "arch/registers.hh" 414661Sksewell@umich.edu#include "base/misc.hh" 424661Sksewell@umich.edu#include "base/trace.hh" 433170Sstever@eecs.umich.edu#include "mem/request.hh" 443170Sstever@eecs.umich.edu 453170Sstever@eecs.umich.edu 463170Sstever@eecs.umich.edunamespace MipsISA 473170Sstever@eecs.umich.edu{ 483170Sstever@eecs.umich.edutemplate <class XC> 493170Sstever@eecs.umich.eduinline void 503170Sstever@eecs.umich.eduhandleLockedRead(XC *xc, Request *req) 513170Sstever@eecs.umich.edu{ 525596Sgblack@eecs.umich.edu xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf); 535596Sgblack@eecs.umich.edu xc->setMiscRegNoEffect(LLFlag, true); 544661Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n", 555715Shsul@eecs.umich.edu req->threadId(), req->getPaddr() & ~0xf); 563170Sstever@eecs.umich.edu} 573170Sstever@eecs.umich.edu 583170Sstever@eecs.umich.edu 593170Sstever@eecs.umich.edutemplate <class XC> 603170Sstever@eecs.umich.eduinline bool 613170Sstever@eecs.umich.eduhandleLockedWrite(XC *xc, Request *req) 623170Sstever@eecs.umich.edu{ 634661Sksewell@umich.edu if (req->isUncacheable()) { 644661Sksewell@umich.edu // Funky Turbolaser mailbox access...don't update 654661Sksewell@umich.edu // result register (see stq_c in decoder.isa) 664661Sksewell@umich.edu req->setExtraData(2); 674661Sksewell@umich.edu } else { 684661Sksewell@umich.edu // standard store conditional 695596Sgblack@eecs.umich.edu bool lock_flag = xc->readMiscRegNoEffect(LLFlag); 705596Sgblack@eecs.umich.edu Addr lock_addr = xc->readMiscRegNoEffect(LLAddr); 714661Sksewell@umich.edu 724661Sksewell@umich.edu if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 734661Sksewell@umich.edu // Lock flag not set or addr mismatch in CPU; 744661Sksewell@umich.edu // don't even bother sending to memory system 754661Sksewell@umich.edu req->setExtraData(0); 765596Sgblack@eecs.umich.edu xc->setMiscRegNoEffect(LLFlag, false); 774661Sksewell@umich.edu 784661Sksewell@umich.edu // the rest of this code is not architectural; 794661Sksewell@umich.edu // it's just a debugging aid to help detect 804661Sksewell@umich.edu // livelock by warning on long sequences of failed 814661Sksewell@umich.edu // store conditionals 824661Sksewell@umich.edu int stCondFailures = xc->readStCondFailures(); 834661Sksewell@umich.edu stCondFailures++; 844661Sksewell@umich.edu xc->setStCondFailures(stCondFailures); 854661Sksewell@umich.edu if (stCondFailures % 10 == 0) { 865714Shsul@eecs.umich.edu warn("%i: context %d: %d consecutive " 874661Sksewell@umich.edu "store conditional failures\n", 885714Shsul@eecs.umich.edu curTick, xc->contextId(), stCondFailures); 894661Sksewell@umich.edu } 904661Sksewell@umich.edu 914661Sksewell@umich.edu if (stCondFailures == 5000) { 924661Sksewell@umich.edu panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n"); 934661Sksewell@umich.edu } 944661Sksewell@umich.edu 954661Sksewell@umich.edu if (!lock_flag){ 964661Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n", 975715Shsul@eecs.umich.edu req->threadId()); 984661Sksewell@umich.edu } else if ((req->getPaddr() & ~0xf) != lock_addr) { 994661Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n", 1005715Shsul@eecs.umich.edu req->threadId()); 1014661Sksewell@umich.edu } 1024661Sksewell@umich.edu // store conditional failed already, so don't issue it to mem 1034661Sksewell@umich.edu return false; 1044661Sksewell@umich.edu } 1054661Sksewell@umich.edu } 1064661Sksewell@umich.edu 1073170Sstever@eecs.umich.edu return true; 1083170Sstever@eecs.umich.edu} 1093170Sstever@eecs.umich.edu 1103170Sstever@eecs.umich.edu 1113170Sstever@eecs.umich.edu} // namespace MipsISA 1123170Sstever@eecs.umich.edu 1133170Sstever@eecs.umich.edu#endif 114