locked_mem.hh revision 5222
13170Sstever@eecs.umich.edu/* 25222Sksewell@umich.edu * Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved 33170Sstever@eecs.umich.edu * 45222Sksewell@umich.edu * This software is part of the M5 simulator. 53170Sstever@eecs.umich.edu * 65222Sksewell@umich.edu * THIS IS A LEGAL AGREEMENT. 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($B!H(BMIPS$B!I(B) is not used in any 185222Sksewell@umich.edu * advertising or publicity pertaining to the use or distribution of 195222Sksewell@umich.edu * this software without specific, written prior authorization. 205222Sksewell@umich.edu * 215222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 225222Sksewell@umich.edu * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 235222Sksewell@umich.edu * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 245222Sksewell@umich.edu * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 255222Sksewell@umich.edu * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 265222Sksewell@umich.edu * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 275222Sksewell@umich.edu * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 285222Sksewell@umich.edu * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 295222Sksewell@umich.edu * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 305222Sksewell@umich.edu * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 315222Sksewell@umich.edu * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 325222Sksewell@umich.edu * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 335222Sksewell@umich.edu * 345222Sksewell@umich.edu * Authors: Steven K. Reinhardt 353170Sstever@eecs.umich.edu */ 363170Sstever@eecs.umich.edu 373170Sstever@eecs.umich.edu#ifndef __ARCH_MIPS_LOCKED_MEM_HH__ 383170Sstever@eecs.umich.edu#define __ARCH_MIPS_LOCKED_MEM_HH__ 393170Sstever@eecs.umich.edu 403170Sstever@eecs.umich.edu/** 413170Sstever@eecs.umich.edu * @file 423170Sstever@eecs.umich.edu * 433170Sstever@eecs.umich.edu * ISA-specific helper functions for locked memory accesses. 443170Sstever@eecs.umich.edu */ 453170Sstever@eecs.umich.edu 464661Sksewell@umich.edu#include "arch/isa_traits.hh" 474661Sksewell@umich.edu#include "base/misc.hh" 484661Sksewell@umich.edu#include "base/trace.hh" 493170Sstever@eecs.umich.edu#include "mem/request.hh" 503170Sstever@eecs.umich.edu 513170Sstever@eecs.umich.edu 523170Sstever@eecs.umich.edunamespace MipsISA 533170Sstever@eecs.umich.edu{ 543170Sstever@eecs.umich.edutemplate <class XC> 553170Sstever@eecs.umich.eduinline void 563170Sstever@eecs.umich.eduhandleLockedRead(XC *xc, Request *req) 573170Sstever@eecs.umich.edu{ 584661Sksewell@umich.edu unsigned tid = req->getThreadNum(); 595222Sksewell@umich.edu xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf, tid); 605222Sksewell@umich.edu xc->setMiscRegNoEffect(LLFlag, true, tid); 614661Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n", 624661Sksewell@umich.edu tid, req->getPaddr() & ~0xf); 633170Sstever@eecs.umich.edu} 643170Sstever@eecs.umich.edu 653170Sstever@eecs.umich.edu 663170Sstever@eecs.umich.edutemplate <class XC> 673170Sstever@eecs.umich.eduinline bool 683170Sstever@eecs.umich.eduhandleLockedWrite(XC *xc, Request *req) 693170Sstever@eecs.umich.edu{ 704661Sksewell@umich.edu unsigned tid = req->getThreadNum(); 714661Sksewell@umich.edu 724661Sksewell@umich.edu if (req->isUncacheable()) { 734661Sksewell@umich.edu // Funky Turbolaser mailbox access...don't update 744661Sksewell@umich.edu // result register (see stq_c in decoder.isa) 754661Sksewell@umich.edu req->setExtraData(2); 764661Sksewell@umich.edu } else { 774661Sksewell@umich.edu // standard store conditional 785222Sksewell@umich.edu bool lock_flag = xc->readMiscRegNoEffect(LLFlag, tid); 795222Sksewell@umich.edu Addr lock_addr = xc->readMiscRegNoEffect(LLAddr, tid); 804661Sksewell@umich.edu 814661Sksewell@umich.edu if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 824661Sksewell@umich.edu // Lock flag not set or addr mismatch in CPU; 834661Sksewell@umich.edu // don't even bother sending to memory system 844661Sksewell@umich.edu req->setExtraData(0); 855222Sksewell@umich.edu xc->setMiscRegNoEffect(LLFlag, false, tid); 864661Sksewell@umich.edu 874661Sksewell@umich.edu // the rest of this code is not architectural; 884661Sksewell@umich.edu // it's just a debugging aid to help detect 894661Sksewell@umich.edu // livelock by warning on long sequences of failed 904661Sksewell@umich.edu // store conditionals 914661Sksewell@umich.edu int stCondFailures = xc->readStCondFailures(); 924661Sksewell@umich.edu stCondFailures++; 934661Sksewell@umich.edu xc->setStCondFailures(stCondFailures); 944661Sksewell@umich.edu if (stCondFailures % 10 == 0) { 954661Sksewell@umich.edu warn("%i: cpu %d: %d consecutive " 964661Sksewell@umich.edu "store conditional failures\n", 974661Sksewell@umich.edu curTick, xc->readCpuId(), stCondFailures); 984661Sksewell@umich.edu } 994661Sksewell@umich.edu 1004661Sksewell@umich.edu if (stCondFailures == 5000) { 1014661Sksewell@umich.edu panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n"); 1024661Sksewell@umich.edu } 1034661Sksewell@umich.edu 1044661Sksewell@umich.edu if (!lock_flag){ 1054661Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n", 1064661Sksewell@umich.edu tid); 1074661Sksewell@umich.edu } else if ((req->getPaddr() & ~0xf) != lock_addr) { 1084661Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n", 1094661Sksewell@umich.edu tid); 1104661Sksewell@umich.edu } 1114661Sksewell@umich.edu // store conditional failed already, so don't issue it to mem 1124661Sksewell@umich.edu return false; 1134661Sksewell@umich.edu } 1144661Sksewell@umich.edu } 1154661Sksewell@umich.edu 1163170Sstever@eecs.umich.edu return true; 1173170Sstever@eecs.umich.edu} 1183170Sstever@eecs.umich.edu 1193170Sstever@eecs.umich.edu 1203170Sstever@eecs.umich.edu} // namespace MipsISA 1213170Sstever@eecs.umich.edu 1223170Sstever@eecs.umich.edu#endif 123