locked_mem.hh revision 4661
13170Sstever@eecs.umich.edu/* 23170Sstever@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 33170Sstever@eecs.umich.edu * All rights reserved. 43170Sstever@eecs.umich.edu * 53170Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 63170Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 73170Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 83170Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 93170Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 103170Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 113170Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 123170Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 133170Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143170Sstever@eecs.umich.edu * this software without specific prior written permission. 153170Sstever@eecs.umich.edu * 163170Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173170Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183170Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193170Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203170Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213170Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223170Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233170Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243170Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253170Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263170Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273170Sstever@eecs.umich.edu * 283170Sstever@eecs.umich.edu * Authors: Steve Reinhardt 293170Sstever@eecs.umich.edu */ 303170Sstever@eecs.umich.edu 313170Sstever@eecs.umich.edu#ifndef __ARCH_MIPS_LOCKED_MEM_HH__ 323170Sstever@eecs.umich.edu#define __ARCH_MIPS_LOCKED_MEM_HH__ 333170Sstever@eecs.umich.edu 343170Sstever@eecs.umich.edu/** 353170Sstever@eecs.umich.edu * @file 363170Sstever@eecs.umich.edu * 373170Sstever@eecs.umich.edu * ISA-specific helper functions for locked memory accesses. 383170Sstever@eecs.umich.edu */ 393170Sstever@eecs.umich.edu 404661Sksewell@umich.edu#include "arch/isa_traits.hh" 414661Sksewell@umich.edu#include "base/misc.hh" 424661Sksewell@umich.edu#include "base/trace.hh" 433170Sstever@eecs.umich.edu#include "mem/request.hh" 443170Sstever@eecs.umich.edu 453170Sstever@eecs.umich.edu 463170Sstever@eecs.umich.edunamespace MipsISA 473170Sstever@eecs.umich.edu{ 483170Sstever@eecs.umich.edutemplate <class XC> 493170Sstever@eecs.umich.eduinline void 503170Sstever@eecs.umich.eduhandleLockedRead(XC *xc, Request *req) 513170Sstever@eecs.umich.edu{ 524661Sksewell@umich.edu unsigned tid = req->getThreadNum(); 534661Sksewell@umich.edu xc->setMiscReg(LLAddr, req->getPaddr() & ~0xf, tid); 544661Sksewell@umich.edu xc->setMiscReg(LLFlag, true, tid); 554661Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to %x.\n", 564661Sksewell@umich.edu tid, req->getPaddr() & ~0xf); 573170Sstever@eecs.umich.edu} 583170Sstever@eecs.umich.edu 593170Sstever@eecs.umich.edu 603170Sstever@eecs.umich.edutemplate <class XC> 613170Sstever@eecs.umich.eduinline bool 623170Sstever@eecs.umich.eduhandleLockedWrite(XC *xc, Request *req) 633170Sstever@eecs.umich.edu{ 644661Sksewell@umich.edu unsigned tid = req->getThreadNum(); 654661Sksewell@umich.edu 664661Sksewell@umich.edu if (req->isUncacheable()) { 674661Sksewell@umich.edu // Funky Turbolaser mailbox access...don't update 684661Sksewell@umich.edu // result register (see stq_c in decoder.isa) 694661Sksewell@umich.edu req->setExtraData(2); 704661Sksewell@umich.edu } else { 714661Sksewell@umich.edu // standard store conditional 724661Sksewell@umich.edu bool lock_flag = xc->readMiscReg(LLFlag, tid); 734661Sksewell@umich.edu Addr lock_addr = xc->readMiscReg(LLAddr, tid); 744661Sksewell@umich.edu 754661Sksewell@umich.edu if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 764661Sksewell@umich.edu // Lock flag not set or addr mismatch in CPU; 774661Sksewell@umich.edu // don't even bother sending to memory system 784661Sksewell@umich.edu req->setExtraData(0); 794661Sksewell@umich.edu xc->setMiscReg(LLFlag, false, tid); 804661Sksewell@umich.edu 814661Sksewell@umich.edu // the rest of this code is not architectural; 824661Sksewell@umich.edu // it's just a debugging aid to help detect 834661Sksewell@umich.edu // livelock by warning on long sequences of failed 844661Sksewell@umich.edu // store conditionals 854661Sksewell@umich.edu int stCondFailures = xc->readStCondFailures(); 864661Sksewell@umich.edu stCondFailures++; 874661Sksewell@umich.edu xc->setStCondFailures(stCondFailures); 884661Sksewell@umich.edu if (stCondFailures % 10 == 0) { 894661Sksewell@umich.edu warn("%i: cpu %d: %d consecutive " 904661Sksewell@umich.edu "store conditional failures\n", 914661Sksewell@umich.edu curTick, xc->readCpuId(), stCondFailures); 924661Sksewell@umich.edu } 934661Sksewell@umich.edu 944661Sksewell@umich.edu if (stCondFailures == 5000) { 954661Sksewell@umich.edu panic("Max (5000) Store Conditional Fails Reached. Check Code For Deadlock.\n"); 964661Sksewell@umich.edu } 974661Sksewell@umich.edu 984661Sksewell@umich.edu if (!lock_flag){ 994661Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional Failed.\n", 1004661Sksewell@umich.edu tid); 1014661Sksewell@umich.edu } else if ((req->getPaddr() & ~0xf) != lock_addr) { 1024661Sksewell@umich.edu DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store Conditional Failed.\n", 1034661Sksewell@umich.edu tid); 1044661Sksewell@umich.edu } 1054661Sksewell@umich.edu // store conditional failed already, so don't issue it to mem 1064661Sksewell@umich.edu return false; 1074661Sksewell@umich.edu } 1084661Sksewell@umich.edu } 1094661Sksewell@umich.edu 1103170Sstever@eecs.umich.edu return true; 1113170Sstever@eecs.umich.edu} 1123170Sstever@eecs.umich.edu 1133170Sstever@eecs.umich.edu 1143170Sstever@eecs.umich.edu} // namespace MipsISA 1153170Sstever@eecs.umich.edu 1163170Sstever@eecs.umich.edu#endif 117