locked_mem.hh revision 12334
13170Sstever@eecs.umich.edu/* 29383SAli.Saidi@ARM.com * Copyright (c) 2012 ARM Limited 39383SAli.Saidi@ARM.com * All rights reserved 49383SAli.Saidi@ARM.com * 59383SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 69383SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 79383SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 89383SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 99383SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 109383SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 119383SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 129383SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 139383SAli.Saidi@ARM.com * 145254Sksewell@umich.edu * Copyright (c) 2006-2007 The Regents of The University of Michigan 155254Sksewell@umich.edu * All rights reserved. 163170Sstever@eecs.umich.edu * 175254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 185254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 195254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 205254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 215254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 225254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 235254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 245254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 255254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 265254Sksewell@umich.edu * this software without specific prior written permission. 273170Sstever@eecs.umich.edu * 285254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393170Sstever@eecs.umich.edu * 405254Sksewell@umich.edu * Authors: Steve Reinhardt 413170Sstever@eecs.umich.edu */ 423170Sstever@eecs.umich.edu 433170Sstever@eecs.umich.edu#ifndef __ARCH_MIPS_LOCKED_MEM_HH__ 443170Sstever@eecs.umich.edu#define __ARCH_MIPS_LOCKED_MEM_HH__ 453170Sstever@eecs.umich.edu 463170Sstever@eecs.umich.edu/** 473170Sstever@eecs.umich.edu * @file 483170Sstever@eecs.umich.edu * 493170Sstever@eecs.umich.edu * ISA-specific helper functions for locked memory accesses. 503170Sstever@eecs.umich.edu */ 513170Sstever@eecs.umich.edu 526329Sgblack@eecs.umich.edu#include "arch/registers.hh" 5312334Sgabeblack@google.com#include "base/logging.hh" 544661Sksewell@umich.edu#include "base/trace.hh" 558232Snate@binkert.org#include "debug/LLSC.hh" 569383SAli.Saidi@ARM.com#include "mem/packet.hh" 573170Sstever@eecs.umich.edu#include "mem/request.hh" 583170Sstever@eecs.umich.edu 593170Sstever@eecs.umich.edunamespace MipsISA 603170Sstever@eecs.umich.edu{ 619383SAli.Saidi@ARM.comtemplate <class XC> 629383SAli.Saidi@ARM.cominline void 639383SAli.Saidi@ARM.comhandleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) 649383SAli.Saidi@ARM.com{ 659383SAli.Saidi@ARM.com if (!xc->readMiscReg(MISCREG_LLFLAG)) 669383SAli.Saidi@ARM.com return; 679383SAli.Saidi@ARM.com 689383SAli.Saidi@ARM.com Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask; 6910574Sandreas.hansson@arm.com Addr snoop_addr = pkt->getAddr() & cacheBlockMask; 709383SAli.Saidi@ARM.com 719383SAli.Saidi@ARM.com if (locked_addr == snoop_addr) 729383SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LLFLAG, false); 739383SAli.Saidi@ARM.com} 749383SAli.Saidi@ARM.com 756378Sgblack@eecs.umich.edu 763170Sstever@eecs.umich.edutemplate <class XC> 773170Sstever@eecs.umich.eduinline void 783170Sstever@eecs.umich.eduhandleLockedRead(XC *xc, Request *req) 793170Sstever@eecs.umich.edu{ 807783SGiacomo.Gabrielli@arm.com xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf); 817783SGiacomo.Gabrielli@arm.com xc->setMiscReg(MISCREG_LLFLAG, true); 8211435Smitch.hayenga@arm.com DPRINTF(LLSC, "[cid:%i]: Load-Link Flag Set & Load-Link" 836378Sgblack@eecs.umich.edu " Address set to %x.\n", 8411435Smitch.hayenga@arm.com req->contextId(), req->getPaddr() & ~0xf); 853170Sstever@eecs.umich.edu} 863170Sstever@eecs.umich.edu 873170Sstever@eecs.umich.edutemplate <class XC> 8810030SAli.Saidi@ARM.cominline void 8910030SAli.Saidi@ARM.comhandleLockedSnoopHit(XC *xc) 9010030SAli.Saidi@ARM.com{ 9110030SAli.Saidi@ARM.com} 9210030SAli.Saidi@ARM.com 9310030SAli.Saidi@ARM.comtemplate <class XC> 943170Sstever@eecs.umich.eduinline bool 9510030SAli.Saidi@ARM.comhandleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask) 963170Sstever@eecs.umich.edu{ 974661Sksewell@umich.edu if (req->isUncacheable()) { 984661Sksewell@umich.edu // Funky Turbolaser mailbox access...don't update 994661Sksewell@umich.edu // result register (see stq_c in decoder.isa) 1004661Sksewell@umich.edu req->setExtraData(2); 1014661Sksewell@umich.edu } else { 1024661Sksewell@umich.edu // standard store conditional 1037783SGiacomo.Gabrielli@arm.com bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG); 1047783SGiacomo.Gabrielli@arm.com Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR); 1054661Sksewell@umich.edu 1064661Sksewell@umich.edu if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { 1074661Sksewell@umich.edu // Lock flag not set or addr mismatch in CPU; 1084661Sksewell@umich.edu // don't even bother sending to memory system 1094661Sksewell@umich.edu req->setExtraData(0); 1107783SGiacomo.Gabrielli@arm.com xc->setMiscReg(MISCREG_LLFLAG, false); 1114661Sksewell@umich.edu 1124661Sksewell@umich.edu // the rest of this code is not architectural; 1134661Sksewell@umich.edu // it's just a debugging aid to help detect 1144661Sksewell@umich.edu // livelock by warning on long sequences of failed 1154661Sksewell@umich.edu // store conditionals 1164661Sksewell@umich.edu int stCondFailures = xc->readStCondFailures(); 1174661Sksewell@umich.edu stCondFailures++; 1184661Sksewell@umich.edu xc->setStCondFailures(stCondFailures); 1196425Sksewell@umich.edu if (stCondFailures % 100000 == 0) { 1205714Shsul@eecs.umich.edu warn("%i: context %d: %d consecutive " 1214661Sksewell@umich.edu "store conditional failures\n", 1227823Ssteve.reinhardt@amd.com curTick(), xc->contextId(), stCondFailures); 1234661Sksewell@umich.edu } 1244661Sksewell@umich.edu 1254661Sksewell@umich.edu if (!lock_flag){ 12611435Smitch.hayenga@arm.com DPRINTF(LLSC, "[cid:%i]: Lock Flag Set, " 1276378Sgblack@eecs.umich.edu "Store Conditional Failed.\n", 12811435Smitch.hayenga@arm.com req->contextId()); 1294661Sksewell@umich.edu } else if ((req->getPaddr() & ~0xf) != lock_addr) { 13011435Smitch.hayenga@arm.com DPRINTF(LLSC, "[cid:%i]: Load-Link Address Mismatch, " 1316378Sgblack@eecs.umich.edu "Store Conditional Failed.\n", 13211435Smitch.hayenga@arm.com req->contextId()); 1334661Sksewell@umich.edu } 1344661Sksewell@umich.edu // store conditional failed already, so don't issue it to mem 1354661Sksewell@umich.edu return false; 1364661Sksewell@umich.edu } 1374661Sksewell@umich.edu } 1384661Sksewell@umich.edu 1393170Sstever@eecs.umich.edu return true; 1403170Sstever@eecs.umich.edu} 1413170Sstever@eecs.umich.edu 14212218Snikos.nikoleris@arm.comtemplate <class XC> 14312218Snikos.nikoleris@arm.cominline void 14412218Snikos.nikoleris@arm.comglobalClearExclusive(XC *xc) 14512218Snikos.nikoleris@arm.com{ 14612218Snikos.nikoleris@arm.com xc->getCpuPtr()->wakeup(xc->threadId()); 14712218Snikos.nikoleris@arm.com} 14812218Snikos.nikoleris@arm.com 1493170Sstever@eecs.umich.edu} // namespace MipsISA 1503170Sstever@eecs.umich.edu 1513170Sstever@eecs.umich.edu#endif 152