locked_mem.hh revision 10030 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006-2007 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#ifndef __ARCH_MIPS_LOCKED_MEM_HH__
44#define __ARCH_MIPS_LOCKED_MEM_HH__
45
46/**
47 * @file
48 *
49 * ISA-specific helper functions for locked memory accesses.
50 */
51
52#include "arch/registers.hh"
53#include "base/misc.hh"
54#include "base/trace.hh"
55#include "debug/LLSC.hh"
56#include "mem/packet.hh"
57#include "mem/request.hh"
58
59namespace MipsISA
60{
61template <class XC>
62inline void
63handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
64{
65    if (!xc->readMiscReg(MISCREG_LLFLAG))
66        return;
67
68    Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
69    Addr snoop_addr = pkt->getAddr();
70
71    assert((cacheBlockMask & snoop_addr) == snoop_addr);
72
73    if (locked_addr == snoop_addr)
74        xc->setMiscReg(MISCREG_LLFLAG, false);
75}
76
77
78template <class XC>
79inline void
80handleLockedRead(XC *xc, Request *req)
81{
82    xc->setMiscReg(MISCREG_LLADDR, req->getPaddr() & ~0xf);
83    xc->setMiscReg(MISCREG_LLFLAG, true);
84    DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
85                  " Address set to %x.\n",
86            req->threadId(), req->getPaddr() & ~0xf);
87}
88
89template <class XC>
90inline void
91handleLockedSnoopHit(XC *xc)
92{
93}
94
95template <class XC>
96inline bool
97handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
98{
99    if (req->isUncacheable()) {
100        // Funky Turbolaser mailbox access...don't update
101        // result register (see stq_c in decoder.isa)
102        req->setExtraData(2);
103    } else {
104        // standard store conditional
105        bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
106        Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
107
108        if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
109            // Lock flag not set or addr mismatch in CPU;
110            // don't even bother sending to memory system
111            req->setExtraData(0);
112            xc->setMiscReg(MISCREG_LLFLAG, false);
113
114            // the rest of this code is not architectural;
115            // it's just a debugging aid to help detect
116            // livelock by warning on long sequences of failed
117            // store conditionals
118            int stCondFailures = xc->readStCondFailures();
119            stCondFailures++;
120            xc->setStCondFailures(stCondFailures);
121            if (stCondFailures % 100000 == 0) {
122                warn("%i: context %d: %d consecutive "
123                     "store conditional failures\n",
124                     curTick(), xc->contextId(), stCondFailures);
125            }
126
127            if (!lock_flag){
128                DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, "
129                              "Store Conditional Failed.\n",
130                        req->threadId());
131            } else if ((req->getPaddr() & ~0xf) != lock_addr) {
132                DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, "
133                              "Store Conditional Failed.\n",
134                        req->threadId());
135            }
136            // store conditional failed already, so don't issue it to mem
137            return false;
138        }
139    }
140
141    return true;
142}
143
144} // namespace MipsISA
145
146#endif
147