system.cc revision 5222
15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved 35222Sksewell@umich.edu * 45222Sksewell@umich.edu * This software is part of the M5 simulator. 55222Sksewell@umich.edu * 65222Sksewell@umich.edu * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 75222Sksewell@umich.edu * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 85222Sksewell@umich.edu * TO THESE TERMS AND CONDITIONS. 95222Sksewell@umich.edu * 105222Sksewell@umich.edu * Permission is granted to use, copy, create derivative works and 115222Sksewell@umich.edu * distribute this software and such derivative works for any purpose, 125222Sksewell@umich.edu * so long as (1) the copyright notice above, this grant of permission, 135222Sksewell@umich.edu * and the disclaimer below appear in all copies and derivative works 145222Sksewell@umich.edu * made, (2) the copyright notice above is augmented as appropriate to 155222Sksewell@umich.edu * reflect the addition of any new copyrightable work in a derivative 165222Sksewell@umich.edu * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3) 175222Sksewell@umich.edu * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any 185222Sksewell@umich.edu * advertising or publicity pertaining to the use or distribution of 195222Sksewell@umich.edu * this software without specific, written prior authorization. 205222Sksewell@umich.edu * 215222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 225222Sksewell@umich.edu * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 235222Sksewell@umich.edu * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 245222Sksewell@umich.edu * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 255222Sksewell@umich.edu * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 265222Sksewell@umich.edu * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 275222Sksewell@umich.edu * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 285222Sksewell@umich.edu * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 295222Sksewell@umich.edu * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 305222Sksewell@umich.edu * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 315222Sksewell@umich.edu * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 325222Sksewell@umich.edu * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 335222Sksewell@umich.edu * 345222Sksewell@umich.edu * 355222Sksewell@umich.edu * Authors: Ali G. Saidi 365222Sksewell@umich.edu * Lisa R. Hsu 375222Sksewell@umich.edu * Nathan L. Binkert 385222Sksewell@umich.edu * Steven K. Reinhardt 395222Sksewell@umich.edu */ 405222Sksewell@umich.edu 415222Sksewell@umich.edu/** 425222Sksewell@umich.edu * @file 435222Sksewell@umich.edu * This code loads the linux kernel, console, pal and patches certain 445222Sksewell@umich.edu * functions. The symbol tables are loaded so that traces can show 455222Sksewell@umich.edu * the executing function and we can skip functions. Various delay 465222Sksewell@umich.edu * loops are skipped and their final values manually computed to speed 475222Sksewell@umich.edu * up boot time. 485222Sksewell@umich.edu */ 495222Sksewell@umich.edu 505222Sksewell@umich.edu#include "arch/vtophys.hh" 515222Sksewell@umich.edu#include "arch/mips/idle_event.hh" 525222Sksewell@umich.edu#include "arch/mips/linux/system.hh" 535222Sksewell@umich.edu#include "arch/mips/linux/threadinfo.hh" 545222Sksewell@umich.edu#include "arch/mips/system.hh" 555222Sksewell@umich.edu#include "base/loader/symtab.hh" 565222Sksewell@umich.edu#include "cpu/thread_context.hh" 575222Sksewell@umich.edu#include "cpu/base.hh" 585222Sksewell@umich.edu#include "dev/platform.hh" 595222Sksewell@umich.edu#include "kern/linux/printk.hh" 605222Sksewell@umich.edu#include "kern/linux/events.hh" 615222Sksewell@umich.edu#include "mem/physical.hh" 625222Sksewell@umich.edu#include "mem/port.hh" 635222Sksewell@umich.edu#include "sim/arguments.hh" 645222Sksewell@umich.edu#include "sim/byteswap.hh" 655222Sksewell@umich.edu 665222Sksewell@umich.eduusing namespace std; 675222Sksewell@umich.eduusing namespace MipsISA; 685222Sksewell@umich.eduusing namespace Linux; 695222Sksewell@umich.edu 705222Sksewell@umich.eduLinuxMipsSystem::LinuxMipsSystem(Params *p) 715222Sksewell@umich.edu : MipsSystem(p) 725222Sksewell@umich.edu{ 735222Sksewell@umich.edu Addr addr = 0; 745222Sksewell@umich.edu 755222Sksewell@umich.edu /** 765222Sksewell@umich.edu * The symbol swapper_pg_dir marks the beginning of the kernel and 775222Sksewell@umich.edu * the location of bootloader passed arguments 785222Sksewell@umich.edu */ 795222Sksewell@umich.edu if (!kernelSymtab->findAddress("swapper_pg_dir", KernelStart)) { 805222Sksewell@umich.edu panic("Could not determine start location of kernel"); 815222Sksewell@umich.edu } 825222Sksewell@umich.edu 835222Sksewell@umich.edu /** 845222Sksewell@umich.edu * Since we aren't using a bootloader, we have to copy the 855222Sksewell@umich.edu * kernel arguments directly into the kernel's memory. 865222Sksewell@umich.edu */ 875222Sksewell@umich.edu virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(), 885222Sksewell@umich.edu params()->boot_osflags.length()+1); 895222Sksewell@umich.edu 905222Sksewell@umich.edu /** 915222Sksewell@umich.edu * find the address of the est_cycle_freq variable and insert it 925222Sksewell@umich.edu * so we don't through the lengthly process of trying to 935222Sksewell@umich.edu * calculated it by using the PIT, RTC, etc. 945222Sksewell@umich.edu */ 955222Sksewell@umich.edu if (kernelSymtab->findAddress("est_cycle_freq", addr)) 965222Sksewell@umich.edu virtPort.write(addr, (uint64_t)(Clock::Frequency / 975222Sksewell@umich.edu p->boot_cpu_frequency)); 985222Sksewell@umich.edu 995222Sksewell@umich.edu 1005222Sksewell@umich.edu /** 1015222Sksewell@umich.edu * EV5 only supports 127 ASNs so we are going to tell the kernel that the 1025222Sksewell@umich.edu * paritiuclar EV6 we have only supports 127 asns. 1035222Sksewell@umich.edu * @todo At some point we should change ev5.hh and the palcode to support 1045222Sksewell@umich.edu * 255 ASNs. 1055222Sksewell@umich.edu */ 1065222Sksewell@umich.edu if (kernelSymtab->findAddress("dp264_mv", addr)) 1075222Sksewell@umich.edu virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127)); 1085222Sksewell@umich.edu else 1095222Sksewell@umich.edu panic("could not find dp264_mv\n"); 1105222Sksewell@umich.edu 1115222Sksewell@umich.edu#ifndef NDEBUG 1125222Sksewell@umich.edu kernelPanicEvent = addKernelFuncEvent<BreakPCEvent>("panic"); 1135222Sksewell@umich.edu if (!kernelPanicEvent) 1145222Sksewell@umich.edu panic("could not find kernel symbol \'panic\'"); 1155222Sksewell@umich.edu 1165222Sksewell@umich.edu#if 0 1175222Sksewell@umich.edu kernelDieEvent = addKernelFuncEvent<BreakPCEvent>("die_if_kernel"); 1185222Sksewell@umich.edu if (!kernelDieEvent) 1195222Sksewell@umich.edu panic("could not find kernel symbol \'die_if_kernel\'"); 1205222Sksewell@umich.edu#endif 1215222Sksewell@umich.edu 1225222Sksewell@umich.edu#endif 1235222Sksewell@umich.edu 1245222Sksewell@umich.edu /** 1255222Sksewell@umich.edu * Any time ide_delay_50ms, calibarte_delay or 1265222Sksewell@umich.edu * determine_cpu_caches is called just skip the 1275222Sksewell@umich.edu * function. Currently determine_cpu_caches only is used put 1285222Sksewell@umich.edu * information in proc, however if that changes in the future we 1295222Sksewell@umich.edu * will have to fill in the cache size variables appropriately. 1305222Sksewell@umich.edu */ 1315222Sksewell@umich.edu 1325222Sksewell@umich.edu skipIdeDelay50msEvent = 1335222Sksewell@umich.edu addKernelFuncEvent<SkipFuncEvent>("ide_delay_50ms"); 1345222Sksewell@umich.edu skipDelayLoopEvent = 1355222Sksewell@umich.edu addKernelFuncEvent<SkipDelayLoopEvent>("calibrate_delay"); 1365222Sksewell@umich.edu skipCacheProbeEvent = 1375222Sksewell@umich.edu addKernelFuncEvent<SkipFuncEvent>("determine_cpu_caches"); 1385222Sksewell@umich.edu debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk"); 1395222Sksewell@umich.edu idleStartEvent = addKernelFuncEvent<IdleStartEvent>("cpu_idle"); 1405222Sksewell@umich.edu 1415222Sksewell@umich.edu // Disable for now as it runs into panic() calls in VPTr methods 1425222Sksewell@umich.edu // (see sim/vptr.hh). Once those bugs are fixed, we can 1435222Sksewell@umich.edu // re-enable, but we should find a better way to turn it on than 1445222Sksewell@umich.edu // using DTRACE(Thread), since looking at a trace flag at tick 0 1455222Sksewell@umich.edu // leads to non-intuitive behavior with --trace-start. 1465222Sksewell@umich.edu if (false && kernelSymtab->findAddress("mips_switch_to", addr)) { 1475222Sksewell@umich.edu printThreadEvent = new PrintThreadInfo(&pcEventQueue, "threadinfo", 1485222Sksewell@umich.edu addr + sizeof(MachInst) * 6); 1495222Sksewell@umich.edu } else { 1505222Sksewell@umich.edu printThreadEvent = NULL; 1515222Sksewell@umich.edu } 1525222Sksewell@umich.edu} 1535222Sksewell@umich.edu 1545222Sksewell@umich.eduLinuxMipsSystem::~LinuxMipsSystem() 1555222Sksewell@umich.edu{ 1565222Sksewell@umich.edu#ifndef NDEBUG 1575222Sksewell@umich.edu delete kernelPanicEvent; 1585222Sksewell@umich.edu#endif 1595222Sksewell@umich.edu delete skipIdeDelay50msEvent; 1605222Sksewell@umich.edu delete skipDelayLoopEvent; 1615222Sksewell@umich.edu delete skipCacheProbeEvent; 1625222Sksewell@umich.edu delete debugPrintkEvent; 1635222Sksewell@umich.edu delete idleStartEvent; 1645222Sksewell@umich.edu delete printThreadEvent; 1655222Sksewell@umich.edu} 1665222Sksewell@umich.edu 1675222Sksewell@umich.edu 1685222Sksewell@umich.eduvoid 1695222Sksewell@umich.eduLinuxMipsSystem::setDelayLoop(ThreadContext *tc) 1705222Sksewell@umich.edu{ 1715222Sksewell@umich.edu Addr addr = 0; 1725222Sksewell@umich.edu if (kernelSymtab->findAddress("loops_per_jiffy", addr)) { 1735222Sksewell@umich.edu Tick cpuFreq = tc->getCpuPtr()->frequency(); 1745222Sksewell@umich.edu Tick intrFreq = platform->intrFrequency(); 1755222Sksewell@umich.edu VirtualPort *vp; 1765222Sksewell@umich.edu 1775222Sksewell@umich.edu vp = tc->getVirtPort(); 1785222Sksewell@umich.edu vp->writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988)); 1795222Sksewell@umich.edu tc->delVirtPort(vp); 1805222Sksewell@umich.edu } 1815222Sksewell@umich.edu} 1825222Sksewell@umich.edu 1835222Sksewell@umich.edu 1845222Sksewell@umich.eduvoid 1855222Sksewell@umich.eduLinuxMipsSystem::SkipDelayLoopEvent::process(ThreadContext *tc) 1865222Sksewell@umich.edu{ 1875222Sksewell@umich.edu SkipFuncEvent::process(tc); 1885222Sksewell@umich.edu // calculate and set loops_per_jiffy 1895222Sksewell@umich.edu ((LinuxMipsSystem *)tc->getSystemPtr())->setDelayLoop(tc); 1905222Sksewell@umich.edu} 1915222Sksewell@umich.edu 1925222Sksewell@umich.eduvoid 1935222Sksewell@umich.eduLinuxMipsSystem::PrintThreadInfo::process(ThreadContext *tc) 1945222Sksewell@umich.edu{ 1955222Sksewell@umich.edu Linux::ThreadInfo ti(tc); 1965222Sksewell@umich.edu 1975222Sksewell@umich.edu DPRINTF(Thread, "Currently Executing Thread %s, pid %d, started at: %d\n", 1985222Sksewell@umich.edu ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart()); 1995222Sksewell@umich.edu} 2005222Sksewell@umich.edu 2015222Sksewell@umich.eduLinuxMipsSystem * 2025222Sksewell@umich.eduLinuxMipsSystemParams::create() 2035222Sksewell@umich.edu{ 2045222Sksewell@umich.edu return new LinuxMipsSystem(this); 2055222Sksewell@umich.edu} 206