isa_traits.hh revision 5268:5bfc53fe60e7
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Korey Sewell
31 *          Jaidev Patwardhan
32 */
33
34#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
35#define __ARCH_MIPS_ISA_TRAITS_HH__
36
37#include "arch/mips/types.hh"
38#include "arch/mips/mips_core_specific.hh"
39#include "config/full_system.hh"
40#include "sim/host.hh"
41
42namespace LittleEndianGuest {};
43
44#define TARGET_MIPS
45
46class StaticInstPtr;
47
48namespace MipsISA
49{
50    using namespace LittleEndianGuest;
51
52    StaticInstPtr decodeInst(ExtMachInst);
53
54    // MIPS DOES have a delay slot
55    #define ISA_HAS_DELAY_SLOT 1
56
57    const Addr PageShift = 13;
58    const Addr PageBytes = ULL(1) << PageShift;
59    const Addr Page_Mask = ~(PageBytes - 1);
60    const Addr PageOffset = PageBytes - 1;
61
62
63    ////////////////////////////////////////////////////////////////////////
64    //
65    //  Translation stuff
66    //
67
68    const Addr PteShift = 3;
69    const Addr NPtePageShift = PageShift - PteShift;
70    const Addr NPtePage = ULL(1) << NPtePageShift;
71    const Addr PteMask = NPtePage - 1;
72
73    //// All 'Mapped' segments go through the TLB
74    //// All other segments are translated by dropping the MSB, to give
75    //// the corresponding physical address
76    // User Segment - Mapped
77    const Addr USegBase = ULL(0x0);
78    const Addr USegEnd = ULL(0x7FFFFFFF);
79
80    // Kernel Segment 0 - Unmapped
81    const Addr KSeg0End = ULL(0x9FFFFFFF);
82    const Addr KSeg0Base =  ULL(0x80000000);
83    const Addr KSeg0Mask = ULL(0x1FFFFFFF);
84
85    // Kernel Segment 1 - Unmapped, Uncached
86    const Addr KSeg1End = ULL(0xBFFFFFFF);
87    const Addr KSeg1Base = ULL(0xA0000000);
88    const Addr KSeg1Mask = ULL(0x1FFFFFFF);
89
90    // Kernel/Supervisor Segment - Mapped
91    const Addr KSSegEnd = ULL(0xDFFFFFFF);
92    const Addr KSSegBase = ULL(0xC0000000);
93
94    // Kernel Segment 3 - Mapped
95    const Addr KSeg3End = ULL(0xFFFFFFFF);
96    const Addr KSeg3Base = ULL(0xE0000000);
97
98
99    // For loading... XXX This maybe could be USegEnd?? --ali
100    const Addr LoadAddrMask = ULL(0xffffffffff);
101
102    inline Addr Phys2K0Seg(Addr addr)
103    {
104   //  if (addr & PAddrUncachedBit43) {
105//         addr &= PAddrUncachedMask;
106//         addr |= PAddrUncachedBit40;
107//     }
108        return addr | KSeg0Base;
109    }
110
111
112    const unsigned VABits = 32;
113    const unsigned PABits = 32; // Is this correct?
114    const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
115    const Addr VAddrUnImplMask = ~VAddrImplMask;
116    inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
117    inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
118    inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
119
120    const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
121
122    ////////////////////////////////////////////////////////////////////////
123    //
124    //  Interrupt levels
125    //
126    enum InterruptLevels
127    {
128        INTLEVEL_SOFTWARE_MIN = 4,
129        INTLEVEL_SOFTWARE_MAX = 19,
130
131        INTLEVEL_EXTERNAL_MIN = 20,
132        INTLEVEL_EXTERNAL_MAX = 34,
133
134        INTLEVEL_IRQ0 = 20,
135        INTLEVEL_IRQ1 = 21,
136        INTINDEX_ETHERNET = 0,
137        INTINDEX_SCSI = 1,
138        INTLEVEL_IRQ2 = 22,
139        INTLEVEL_IRQ3 = 23,
140
141        INTLEVEL_SERIAL = 33,
142
143        NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
144    };
145
146
147    // MIPS modes
148    enum mode_type
149    {
150        mode_kernel = 0,		// kernel
151        mode_supervisor = 1,	// supervisor
152        mode_user = 2,		// user mode
153        mode_debug = 3,         // debug mode
154        mode_number			// number of modes
155    };
156
157  inline mode_type getOperatingMode(MiscReg Stat)
158  {
159    if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
160      return mode_kernel;
161    else{
162      if((Stat & 0x18) == 0x8)
163        return mode_supervisor;
164      else if((Stat & 0x18) == 0x10)
165        return mode_user;
166      else return mode_number;
167    }
168  }
169
170
171    // return a no-op instruction... used for instruction fetch faults
172    const ExtMachInst NoopMachInst = 0x00000000;
173
174    // Constants Related to the number of registers
175    const int NumIntArchRegs = 32;
176    const int NumIntSpecialRegs = 9;
177    const int NumFloatArchRegs = 32;
178    const int NumFloatSpecialRegs = 5;
179
180    const int NumShadowRegSets = 16; // Maximum number of shadow register sets
181    const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs;        //HI & LO Regs
182    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
183
184    // Static instruction parameters
185    const int MaxInstSrcRegs = 10;
186    const int MaxInstDestRegs = 8;
187
188    // semantically meaningful register indices
189    const int ZeroReg = 0;
190    const int AssemblerReg = 1;
191    const int ReturnValueReg = 2;
192    const int ReturnValueReg1 = 2;
193    const int ReturnValueReg2 = 3;
194    const int ArgumentReg0 = 4;
195    const int ArgumentReg1 = 5;
196    const int ArgumentReg2 = 6;
197    const int ArgumentReg3 = 7;
198    const int KernelReg0 = 26;
199    const int KernelReg1 = 27;
200    const int GlobalPointerReg = 28;
201    const int StackPointerReg = 29;
202    const int FramePointerReg = 30;
203    const int ReturnAddressReg = 31;
204
205    const int ArgumentReg[] = {4, 5, 6, 7};
206    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
207
208    const int SyscallNumReg = ReturnValueReg1;
209    const int SyscallPseudoReturnReg = ReturnValueReg2;
210    const int SyscallSuccessReg = ArgumentReg3;
211
212    const int LogVMPageSize = 13;	// 8K bytes
213    const int VMPageSize = (1 << LogVMPageSize);
214
215    const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
216
217    const int MachineBytes = 4;
218    const int WordBytes = 4;
219    const int HalfwordBytes = 2;
220    const int ByteBytes = 1;
221
222    const int ANNOTE_NONE = 0;
223    const uint32_t ITOUCH_ANNOTE = 0xffffffff;
224
225    // These help enumerate all the registers for dependence tracking.
226    const int FP_Base_DepTag = NumIntRegs;
227    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
228
229    // Enumerate names for 'Control' Registers in the CPU
230    // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
231    // (Register Number-Register Select) Summary of Register
232    //------------------------------------------------------
233    // The first set of names classify the CP0 names as Register Banks
234    // for easy indexing when using the 'RD + SEL' index combination
235    // in CP0 instructions.
236    enum MiscRegTags {
237        Index = Ctrl_Base_DepTag + 0,       //Bank 0: 0 - 3
238        MVPControl,
239        MVPConf0,
240        MVPConf1,
241
242        CP0_Random = Ctrl_Base_DepTag + 8,      //Bank 1: 8 - 15
243        VPEControl,
244        VPEConf0,
245        VPEConf1,
246        YQMask,
247        VPESchedule,
248        VPEScheFBack,
249        VPEOpt,
250
251        EntryLo0 = Ctrl_Base_DepTag + 16,   //Bank 2: 16 - 23
252        TCStatus,
253        TCBind,
254        TCRestart,
255        TCHalt,
256        TCContext,
257        TCSchedule,
258        TCScheFBack,
259
260        EntryLo1 = Ctrl_Base_DepTag + 24,   // Bank 3: 24
261
262        Context = Ctrl_Base_DepTag + 32,    // Bank 4: 32 - 33
263        ContextConfig,
264
265        PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
266        PageGrain = Ctrl_Base_DepTag + 41,
267
268        Wired = Ctrl_Base_DepTag + 48,          //Bank 6:48-55
269        SRSConf0,
270        SRSConf1,
271        SRSConf2,
272        SRSConf3,
273        SRSConf4,
274
275        HWRena = Ctrl_Base_DepTag + 56,         //Bank 7: 56-63
276
277        BadVAddr = Ctrl_Base_DepTag + 64,       //Bank 8: 64-71
278
279        Count = Ctrl_Base_DepTag + 72,          //Bank 9: 72-79
280
281        EntryHi = Ctrl_Base_DepTag + 80,        //Bank 10: 80-87
282
283        Compare = Ctrl_Base_DepTag + 88,        //Bank 11: 88-95
284
285        Status = Ctrl_Base_DepTag + 96,         //Bank 12: 96-103
286        IntCtl,
287        SRSCtl,
288        SRSMap,
289
290        Cause = Ctrl_Base_DepTag + 104,         //Bank 13: 104-111
291
292        EPC = Ctrl_Base_DepTag + 112,           //Bank 14: 112-119
293
294        PRId = Ctrl_Base_DepTag + 120,          //Bank 15: 120-127,
295        EBase,
296
297        Config = Ctrl_Base_DepTag + 128,        //Bank 16: 128-135
298        Config1,
299        Config2,
300        Config3,
301        Config4,
302        Config5,
303        Config6,
304        Config7,
305
306
307        LLAddr = Ctrl_Base_DepTag + 136,        //Bank 17: 136-143
308
309        WatchLo0 = Ctrl_Base_DepTag + 144,      //Bank 18: 144-151
310        WatchLo1,
311        WatchLo2,
312        WatchLo3,
313        WatchLo4,
314        WatchLo5,
315        WatchLo6,
316        WatchLo7,
317
318        WatchHi0 = Ctrl_Base_DepTag + 152,     //Bank 19: 152-159
319        WatchHi1,
320        WatchHi2,
321        WatchHi3,
322        WatchHi4,
323        WatchHi5,
324        WatchHi6,
325        WatchHi7,
326
327        XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
328
329                           //Bank 21: 168-175
330
331                           //Bank 22: 176-183
332
333        Debug = Ctrl_Base_DepTag + 184,       //Bank 23: 184-191
334        TraceControl1,
335        TraceControl2,
336        UserTraceData,
337        TraceBPC,
338
339        DEPC = Ctrl_Base_DepTag + 192,        //Bank 24: 192-199
340
341        PerfCnt0 = Ctrl_Base_DepTag + 200,    //Bank 25: 200-207
342        PerfCnt1,
343        PerfCnt2,
344        PerfCnt3,
345        PerfCnt4,
346        PerfCnt5,
347        PerfCnt6,
348        PerfCnt7,
349
350        ErrCtl = Ctrl_Base_DepTag + 208,      //Bank 26: 208-215
351
352        CacheErr0 = Ctrl_Base_DepTag + 216,   //Bank 27: 216-223
353        CacheErr1,
354        CacheErr2,
355        CacheErr3,
356
357        TagLo0 = Ctrl_Base_DepTag + 224,      //Bank 28: 224-231
358        DataLo1,
359        TagLo2,
360        DataLo3,
361        TagLo4,
362        DataLo5,
363        TagLo6,
364        DataLo7,
365
366        TagHi0 = Ctrl_Base_DepTag + 232,      //Bank 29: 232-239
367        DataHi1,
368        TagHi2,
369        DataHi3,
370        TagHi4,
371        DataHi5,
372        TagHi6,
373        DataHi7,
374
375
376        ErrorEPC = Ctrl_Base_DepTag + 240,    //Bank 30: 240-247
377
378        DESAVE = Ctrl_Base_DepTag + 248,       //Bank 31: 248-256
379
380        LLFlag = Ctrl_Base_DepTag + 257,
381
382        NumControlRegs
383    };
384
385    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
386
387    const int NumMiscRegs = NumControlRegs;
388
389    const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
390
391
392};
393
394using namespace MipsISA;
395
396#endif // __ARCH_MIPS_ISA_TRAITS_HH__
397