isa_traits.hh revision 5228:b08c9c42907a
14762Snate@binkert.org/* 27534Ssteve.reinhardt@amd.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 34762Snate@binkert.org * All rights reserved. 44762Snate@binkert.org * 54762Snate@binkert.org * Redistribution and use in source and binary forms, with or without 64762Snate@binkert.org * modification, are permitted provided that the following conditions are 74762Snate@binkert.org * met: redistributions of source code must retain the above copyright 84762Snate@binkert.org * notice, this list of conditions and the following disclaimer; 94762Snate@binkert.org * redistributions in binary form must reproduce the above copyright 104762Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 114762Snate@binkert.org * documentation and/or other materials provided with the distribution; 124762Snate@binkert.org * neither the name of the copyright holders nor the names of its 134762Snate@binkert.org * contributors may be used to endorse or promote products derived from 144762Snate@binkert.org * this software without specific prior written permission. 154762Snate@binkert.org * 164762Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174762Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184762Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194762Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204762Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214762Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224762Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234762Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244762Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254762Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264762Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274762Snate@binkert.org * 284762Snate@binkert.org * Authors: Gabe Black 294762Snate@binkert.org * Korey Sewell 304762Snate@binkert.org */ 314762Snate@binkert.org 324762Snate@binkert.org#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 334762Snate@binkert.org#define __ARCH_MIPS_ISA_TRAITS_HH__ 344762Snate@binkert.org 354762Snate@binkert.org#include "arch/mips/max_inst_regs.hh" 364762Snate@binkert.org#include "arch/mips/types.hh" 376001Snate@binkert.org#include "sim/host.hh" 386001Snate@binkert.org 394762Snate@binkert.orgnamespace LittleEndianGuest {}; 404762Snate@binkert.org 414851Snate@binkert.org#define TARGET_MIPS 427525Ssteve.reinhardt@amd.com 434762Snate@binkert.orgclass StaticInstPtr; 446654Snate@binkert.org 456654Snate@binkert.orgnamespace MipsISA 466654Snate@binkert.org{ 474762Snate@binkert.org using namespace LittleEndianGuest; 484762Snate@binkert.org using MipsISAInst::MaxInstSrcRegs; 497531Ssteve.reinhardt@amd.com using MipsISAInst::MaxInstDestRegs; 508234Snate@binkert.org 518234Snate@binkert.org StaticInstPtr decodeInst(ExtMachInst); 527525Ssteve.reinhardt@amd.com 537525Ssteve.reinhardt@amd.com // MIPS DOES a delay slot 547525Ssteve.reinhardt@amd.com #define ISA_HAS_DELAY_SLOT 1 557525Ssteve.reinhardt@amd.com 567525Ssteve.reinhardt@amd.com const Addr PageShift = 13; 574762Snate@binkert.org const Addr PageBytes = ULL(1) << PageShift; 584762Snate@binkert.org const Addr PageMask = ~(PageBytes - 1); 594762Snate@binkert.org const Addr PageOffset = PageBytes - 1; 607528Ssteve.reinhardt@amd.com 617528Ssteve.reinhardt@amd.com // return a no-op instruction... used for instruction fetch faults 627528Ssteve.reinhardt@amd.com const ExtMachInst NoopMachInst = 0x00000000; 637528Ssteve.reinhardt@amd.com 647527Ssteve.reinhardt@amd.com // Constants Related to the number of registers 657527Ssteve.reinhardt@amd.com const int NumIntArchRegs = 32; 665037Smilesck@eecs.umich.edu const int NumIntSpecialRegs = 9; 675773Snate@binkert.org const int NumFloatArchRegs = 32; 685773Snate@binkert.org const int NumFloatSpecialRegs = 5; 697527Ssteve.reinhardt@amd.com 707527Ssteve.reinhardt@amd.com // semantically meaningful register indices 717527Ssteve.reinhardt@amd.com const int ZeroReg = 0; 725773Snate@binkert.org const int AssemblerReg = 1; 734762Snate@binkert.org const int ReturnValueReg = 2; 744762Snate@binkert.org const int ReturnValueReg1 = 2; 756001Snate@binkert.org const int ReturnValueReg2 = 3; 764762Snate@binkert.org 774762Snate@binkert.org const int ArgumentReg[] = {4, 5, 6, 7}; 787527Ssteve.reinhardt@amd.com const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 797527Ssteve.reinhardt@amd.com 804762Snate@binkert.org const int KernelReg0 = 26; 814762Snate@binkert.org const int KernelReg1 = 27; 827527Ssteve.reinhardt@amd.com const int GlobalPointerReg = 28; 834762Snate@binkert.org const int StackPointerReg = 29; 844762Snate@binkert.org const int FramePointerReg = 30; 857527Ssteve.reinhardt@amd.com const int ReturnAddressReg = 31; 867527Ssteve.reinhardt@amd.com 874762Snate@binkert.org const int SyscallNumReg = ReturnValueReg1; 886001Snate@binkert.org const int SyscallPseudoReturnReg = ReturnValueReg2; 896001Snate@binkert.org const int SyscallSuccessReg = ArgumentReg[3]; 904762Snate@binkert.org 917531Ssteve.reinhardt@amd.com const int LogVMPageSize = 13; // 8K bytes 927531Ssteve.reinhardt@amd.com const int VMPageSize = (1 << LogVMPageSize); 937532Ssteve.reinhardt@amd.com 947532Ssteve.reinhardt@amd.com const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 957532Ssteve.reinhardt@amd.com 967531Ssteve.reinhardt@amd.com const int MachineBytes = 4; 977532Ssteve.reinhardt@amd.com const int WordBytes = 4; 987532Ssteve.reinhardt@amd.com const int HalfwordBytes = 2; 997531Ssteve.reinhardt@amd.com const int ByteBytes = 1; 1004762Snate@binkert.org 1016001Snate@binkert.org const int ANNOTE_NONE = 0; 1024762Snate@binkert.org const uint32_t ITOUCH_ANNOTE = 0xffffffff; 1034762Snate@binkert.org 1044762Snate@binkert.org // Enumerate names for 'Control' Registers in the CPU 1054762Snate@binkert.org // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 1064762Snate@binkert.org // (Register Number-Register Select) Summary of Register 1074762Snate@binkert.org //------------------------------------------------------ 1084762Snate@binkert.org // The first set of names classify the CP0 names as Register Banks 1094762Snate@binkert.org // for easy indexing when using the 'RD + SEL' index combination 1104762Snate@binkert.org // in CP0 instructions. 1114762Snate@binkert.org enum MiscRegTags { 1124762Snate@binkert.org Index = 0, //Bank 0: 0 - 3 1134762Snate@binkert.org MVPControl, 1144762Snate@binkert.org MVPConf0, 1154762Snate@binkert.org MVPConf1, 1164762Snate@binkert.org 1174762Snate@binkert.org Random = 8, //Bank 1: 8 - 15 1184762Snate@binkert.org VPEControl, 1197527Ssteve.reinhardt@amd.com VPEConf0, 1207527Ssteve.reinhardt@amd.com VPEConf1, 1214762Snate@binkert.org YQMask, 1224762Snate@binkert.org VPESchedule, 1234762Snate@binkert.org VPEScheFBack, 1244762Snate@binkert.org VPEOpt, 1254762Snate@binkert.org 1264762Snate@binkert.org EntryLo0 = 16, //Bank 2: 16 - 23 1274762Snate@binkert.org TCStatus, 1284762Snate@binkert.org TCBind, 1294762Snate@binkert.org TCRestart, 1304762Snate@binkert.org TCHalt, 1317823Ssteve.reinhardt@amd.com TCContext, 1324762Snate@binkert.org TCSchedule, 1334762Snate@binkert.org TCScheFBack, 1344762Snate@binkert.org 1354762Snate@binkert.org EntryLo1 = 24, // Bank 3: 24 1364762Snate@binkert.org 1374762Snate@binkert.org Context = 32, // Bank 4: 32 - 33 1384762Snate@binkert.org ContextConfig, 1394762Snate@binkert.org 1404762Snate@binkert.org //PageMask = 40, //Bank 5: 40 - 41 1414762Snate@binkert.org PageGrain = 41, 1424762Snate@binkert.org 1434762Snate@binkert.org Wired = 48, //Bank 6:48-55 1444762Snate@binkert.org SRSConf0, 1454762Snate@binkert.org SRSConf1, 1464762Snate@binkert.org SRSConf2, 1474762Snate@binkert.org SRSConf3, 1484762Snate@binkert.org SRSConf4, 1494762Snate@binkert.org 1504762Snate@binkert.org HWRena = 56, //Bank 7: 56-63 1514762Snate@binkert.org 1527527Ssteve.reinhardt@amd.com BadVAddr = 64, //Bank 8: 64-71 1534762Snate@binkert.org 1547527Ssteve.reinhardt@amd.com Count = 72, //Bank 9: 72-79 1557527Ssteve.reinhardt@amd.com 1564762Snate@binkert.org EntryHi = 80, //Bank 10: 80-87 1574762Snate@binkert.org 1584762Snate@binkert.org Compare = 88, //Bank 11: 88-95 1594762Snate@binkert.org 1604762Snate@binkert.org Status = 96, //Bank 12: 96-103 1614762Snate@binkert.org IntCtl, 1624762Snate@binkert.org SRSCtl, 1637527Ssteve.reinhardt@amd.com SRSMap, 1644762Snate@binkert.org 1657525Ssteve.reinhardt@amd.com Cause = 104, //Bank 13: 104-111 1667525Ssteve.reinhardt@amd.com 1674762Snate@binkert.org EPC = 112, //Bank 14: 112-119 1684762Snate@binkert.org 1694762Snate@binkert.org PRId = 120, //Bank 15: 120-127, 1704762Snate@binkert.org EBase, 1714859Snate@binkert.org 1724762Snate@binkert.org Config = 128, //Bank 16: 128-135 1734762Snate@binkert.org Config1, 1744762Snate@binkert.org Config2, 1754762Snate@binkert.org Config3, 1764762Snate@binkert.org Config4, 1774762Snate@binkert.org Config5, 1784945Snate@binkert.org Config6, 1794762Snate@binkert.org Config7, 1804762Snate@binkert.org 1817527Ssteve.reinhardt@amd.com 1827527Ssteve.reinhardt@amd.com LLAddr = 136, //Bank 17: 136-143 1834762Snate@binkert.org 1844762Snate@binkert.org WatchLo0 = 144, //Bank 18: 144-151 1854762Snate@binkert.org WatchLo1, 1864762Snate@binkert.org WatchLo2, 1874762Snate@binkert.org WatchLo3, 1884762Snate@binkert.org WatchLo4, 1894945Snate@binkert.org WatchLo5, 1904762Snate@binkert.org WatchLo6, 1914762Snate@binkert.org WatchLo7, 1927527Ssteve.reinhardt@amd.com 1937527Ssteve.reinhardt@amd.com WatchHi0 = 152, //Bank 19: 152-159 1944762Snate@binkert.org WatchHi1, 1954762Snate@binkert.org WatchHi2, 1964762Snate@binkert.org WatchHi3, 1974762Snate@binkert.org WatchHi4, 1984762Snate@binkert.org WatchHi5, 1994946Snate@binkert.org WatchHi6, 2004946Snate@binkert.org WatchHi7, 2014762Snate@binkert.org 2024762Snate@binkert.org XCContext64 = 160, //Bank 20: 160-167 2034946Snate@binkert.org 2044946Snate@binkert.org //Bank 21: 168-175 2054946Snate@binkert.org 2064946Snate@binkert.org //Bank 22: 176-183 2074946Snate@binkert.org 2084762Snate@binkert.org Debug = 184, //Bank 23: 184-191 2094946Snate@binkert.org TraceControl1, 2104946Snate@binkert.org TraceControl2, 2114946Snate@binkert.org UserTraceData, 2124762Snate@binkert.org TraceBPC, 2134946Snate@binkert.org 2144946Snate@binkert.org DEPC = 192, //Bank 24: 192-199 2155523Snate@binkert.org 2165523Snate@binkert.org PerfCnt0 = 200, //Bank 25: 200-207 217 PerfCnt1, 218 PerfCnt2, 219 PerfCnt3, 220 PerfCnt4, 221 PerfCnt5, 222 PerfCnt6, 223 PerfCnt7, 224 225 ErrCtl = 208, //Bank 26: 208-215 226 227 CacheErr0 = 216, //Bank 27: 216-223 228 CacheErr1, 229 CacheErr2, 230 CacheErr3, 231 232 TagLo0 = 224, //Bank 28: 224-231 233 DataLo1, 234 TagLo2, 235 DataLo3, 236 TagLo4, 237 DataLo5, 238 TagLo6, 239 DataLo7, 240 241 TagHi0 = 232, //Bank 29: 232-239 242 DataHi1, 243 TagHi2, 244 DataHi3, 245 TagHi4, 246 DataHi5, 247 TagHi6, 248 DataHi7, 249 250 251 ErrorEPC = 240, //Bank 30: 240-247 252 253 DESAVE = 248, //Bank 31: 248-256 254 255 LLFlag = 257, 256 257 NumControlRegs 258 }; 259 260 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 261 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 262 const int NumMiscRegs = NumControlRegs; 263 264 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 265 266 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 267 268 // These help enumerate all the registers for dependence tracking. 269 const int FP_Base_DepTag = NumIntRegs; 270 const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 271}; 272 273using namespace MipsISA; 274 275#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 276