isa_traits.hh revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
30#define __ARCH_MIPS_ISA_TRAITS_HH__
31
32#include "arch/mips/constants.hh"
33#include "arch/mips/types.hh"
34#include "arch/mips/regfile/regfile.hh"
35#include "arch/mips/faults.hh"
36#include "arch/mips/utility.hh"
37#include "base/misc.hh"
38#include "config/full_system.hh"
39#include "sim/byteswap.hh"
40#include "sim/host.hh"
41#include "sim/faults.hh"
42
43#include <vector>
44
45class FastCPU;
46class FullCPU;
47class Checkpoint;
48class ExecContext;
49
50namespace LittleEndianGuest {};
51
52#define TARGET_MIPS
53
54class StaticInst;
55class StaticInstPtr;
56
57namespace MIPS34K {
58int DTB_ASN_ASN(uint64_t reg);
59int ITB_ASN_ASN(uint64_t reg);
60};
61
62#if !FULL_SYSTEM
63class SyscallReturn {
64        public:
65           template <class T>
66           SyscallReturn(T v, bool s)
67           {
68               retval = (uint32_t)v;
69               success = s;
70           }
71
72           template <class T>
73           SyscallReturn(T v)
74           {
75               success = (v >= 0);
76               retval = (uint32_t)v;
77           }
78
79           ~SyscallReturn() {}
80
81           SyscallReturn& operator=(const SyscallReturn& s) {
82               retval = s.retval;
83               success = s.success;
84               return *this;
85           }
86
87           bool successful() { return success; }
88           uint64_t value() { return retval; }
89
90
91       private:
92           uint64_t retval;
93           bool success;
94};
95#endif
96
97namespace MipsISA
98{
99    using namespace LittleEndianGuest;
100
101    static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
102    {
103        if (return_value.successful()) {
104            // no error
105            regs->setIntReg(SyscallSuccessReg, 0);
106            regs->setIntReg(ReturnValueReg1, return_value.value());
107        } else {
108            // got an error, return details
109            regs->setIntReg(SyscallSuccessReg, (IntReg) -1);
110            regs->setIntReg(ReturnValueReg1, -return_value.value());
111        }
112    }
113
114    StaticInstPtr decodeInst(ExtMachInst);
115
116    static inline ExtMachInst
117    makeExtMI(MachInst inst, const uint64_t &pc) {
118#if FULL_SYSTEM
119        ExtMachInst ext_inst = inst;
120        if (pc && 0x1)
121            return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
122        else
123            return ext_inst;
124#else
125        return ExtMachInst(inst);
126#endif
127    }
128
129    /**
130     * Function to insure ISA semantics about 0 registers.
131     * @param xc The execution context.
132     */
133    template <class XC>
134    void zeroRegisters(XC *xc);
135
136    const Addr MaxAddr = (Addr)-1;
137
138    void copyRegs(ExecContext *src, ExecContext *dest);
139
140    uint64_t fpConvert(double fp_val, ConvertType cvt_type);
141    double roundFP(double val, int digits);
142    double truncFP(double val);
143    bool getFPConditionCode(uint32_t fcsr_reg, int cc);
144    uint32_t makeCCVector(uint32_t fcsr, int num, bool val);
145
146    // Machine operations
147
148    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
149                               int regnum);
150
151    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
152                                  int regnum);
153
154#if 0
155    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
156                                     const RegFile &regs);
157
158    static void unserializeSpecialRegs(const IniFile *db,
159                                       const std::string &category,
160                                       ConfigNode *node,
161                                       RegFile &regs);
162#endif
163
164    static inline Addr alignAddress(const Addr &addr,
165                                         unsigned int nbytes) {
166        return (addr & ~(nbytes - 1));
167    }
168
169    // Instruction address compression hooks
170    static inline Addr realPCToFetchPC(const Addr &addr) {
171        return addr;
172    }
173
174    static inline Addr fetchPCToRealPC(const Addr &addr) {
175        return addr;
176    }
177
178    // the size of "fetched" instructions (not necessarily the size
179    // of real instructions for PISA)
180    static inline size_t fetchInstSize() {
181        return sizeof(MachInst);
182    }
183
184    static inline MachInst makeRegisterCopy(int dest, int src) {
185        panic("makeRegisterCopy not implemented");
186        return 0;
187    }
188
189};
190
191#if FULL_SYSTEM
192
193#include "arch/mips/mips34k.hh"
194
195#endif
196
197using namespace MipsISA;
198
199#endif // __ARCH_MIPS_ISA_TRAITS_HH__
200