isa_traits.hh revision 12408:51e487705276 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Korey Sewell
31 *          Jaidev Patwardhan
32 */
33
34#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
35#define __ARCH_MIPS_ISA_TRAITS_HH__
36
37#include "arch/mips/types.hh"
38#include "base/types.hh"
39#include "cpu/static_inst_fwd.hh"
40
41namespace LittleEndianGuest {}
42
43namespace MipsISA
44{
45
46using namespace LittleEndianGuest;
47
48StaticInstPtr decodeInst(ExtMachInst);
49
50// MIPS DOES have a delay slot
51#define ISA_HAS_DELAY_SLOT 1
52
53const Addr PageShift = 13;
54const Addr PageBytes = ULL(1) << PageShift;
55const Addr Page_Mask = ~(PageBytes - 1);
56const Addr PageOffset = PageBytes - 1;
57
58
59////////////////////////////////////////////////////////////////////////
60//
61//  Translation stuff
62//
63
64const Addr PteShift = 3;
65const Addr NPtePageShift = PageShift - PteShift;
66const Addr NPtePage = ULL(1) << NPtePageShift;
67const Addr PteMask = NPtePage - 1;
68
69//// All 'Mapped' segments go through the TLB
70//// All other segments are translated by dropping the MSB, to give
71//// the corresponding physical address
72// User Segment - Mapped
73const Addr USegBase = ULL(0x0);
74const Addr USegEnd = ULL(0x7FFFFFFF);
75
76// Kernel Segment 0 - Unmapped
77const Addr KSeg0End = ULL(0x9FFFFFFF);
78const Addr KSeg0Base =  ULL(0x80000000);
79const Addr KSeg0Mask = ULL(0x1FFFFFFF);
80
81// Kernel Segment 1 - Unmapped, Uncached
82const Addr KSeg1End = ULL(0xBFFFFFFF);
83const Addr KSeg1Base = ULL(0xA0000000);
84const Addr KSeg1Mask = ULL(0x1FFFFFFF);
85
86// Kernel/Supervisor Segment - Mapped
87const Addr KSSegEnd = ULL(0xDFFFFFFF);
88const Addr KSSegBase = ULL(0xC0000000);
89
90// Kernel Segment 3 - Mapped
91const Addr KSeg3End = ULL(0xFFFFFFFF);
92const Addr KSeg3Base = ULL(0xE0000000);
93
94
95inline Addr Phys2K0Seg(Addr addr)
96{
97    return addr | KSeg0Base;
98}
99
100
101const unsigned VABits = 32;
102const unsigned PABits = 32; // Is this correct?
103const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
104const Addr VAddrUnImplMask = ~VAddrImplMask;
105inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
106inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
107inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
108
109const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
110
111////////////////////////////////////////////////////////////////////////
112//
113//  Interrupt levels
114//
115enum InterruptLevels
116{
117    INTLEVEL_SOFTWARE_MIN = 4,
118    INTLEVEL_SOFTWARE_MAX = 19,
119
120    INTLEVEL_EXTERNAL_MIN = 20,
121    INTLEVEL_EXTERNAL_MAX = 34,
122
123    INTLEVEL_IRQ0 = 20,
124    INTLEVEL_IRQ1 = 21,
125    INTINDEX_ETHERNET = 0,
126    INTINDEX_SCSI = 1,
127    INTLEVEL_IRQ2 = 22,
128    INTLEVEL_IRQ3 = 23,
129
130    INTLEVEL_SERIAL = 33,
131
132    NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
133};
134
135// MIPS modes
136enum mode_type
137{
138    mode_kernel = 0,        // kernel
139    mode_supervisor = 1,    // supervisor
140    mode_user = 2,          // user mode
141    mode_debug = 3,         // debug mode
142    mode_number             // number of modes
143};
144
145const int ANNOTE_NONE = 0;
146const uint32_t ITOUCH_ANNOTE = 0xffffffff;
147
148const bool HasUnalignedMemAcc = true;
149
150const bool CurThreadInfoImplemented = false;
151const int CurThreadInfoReg = -1;
152
153} // namespace MipsISA
154
155#endif // __ARCH_MIPS_ISA_TRAITS_HH__
156