isa_traits.hh revision 2972
12023SN/A/* 22023SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32023SN/A * All rights reserved. 42023SN/A * 52023SN/A * Redistribution and use in source and binary forms, with or without 62023SN/A * modification, are permitted provided that the following conditions are 72023SN/A * met: redistributions of source code must retain the above copyright 82023SN/A * notice, this list of conditions and the following disclaimer; 92023SN/A * redistributions in binary form must reproduce the above copyright 102023SN/A * notice, this list of conditions and the following disclaimer in the 112023SN/A * documentation and/or other materials provided with the distribution; 122023SN/A * neither the name of the copyright holders nor the names of its 132023SN/A * contributors may be used to endorse or promote products derived from 142023SN/A * this software without specific prior written permission. 152023SN/A * 162023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262023SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Korey Sewell 302023SN/A */ 312023SN/A 322028SN/A#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 332028SN/A#define __ARCH_MIPS_ISA_TRAITS_HH__ 342023SN/A 352597SN/A#include "arch/mips/types.hh" 362023SN/A#include "sim/host.hh" 372023SN/A 382239SN/Anamespace LittleEndianGuest {}; 392239SN/A 402028SN/A#define TARGET_MIPS 412023SN/A 422131SN/Aclass StaticInstPtr; 432023SN/A 442131SN/Anamespace MipsISA 452023SN/A{ 462525SN/A using namespace LittleEndianGuest; 472525SN/A 482447SN/A StaticInstPtr decodeInst(ExtMachInst); 492023SN/A 502972Sgblack@eecs.umich.edu const Addr PageShift = 13; 512972Sgblack@eecs.umich.edu const Addr PageBytes = ULL(1) << PageShift; 522972Sgblack@eecs.umich.edu const Addr PageMask = ~(PageBytes - 1); 532972Sgblack@eecs.umich.edu const Addr PageOffset = PageBytes - 1; 542239SN/A 552972Sgblack@eecs.umich.edu // return a no-op instruction... used for instruction fetch faults 562972Sgblack@eecs.umich.edu const ExtMachInst NoopMachInst = 0x00000000; 572131SN/A 582972Sgblack@eecs.umich.edu // Constants Related to the number of registers 592972Sgblack@eecs.umich.edu const int NumIntArchRegs = 32; 602972Sgblack@eecs.umich.edu const int NumIntSpecialRegs = 2; 612972Sgblack@eecs.umich.edu const int NumFloatArchRegs = 32; 622972Sgblack@eecs.umich.edu const int NumFloatSpecialRegs = 5; 632972Sgblack@eecs.umich.edu const int NumControlRegs = 265; 642972Sgblack@eecs.umich.edu const int NumInternalProcRegs = 0; 652131SN/A 662972Sgblack@eecs.umich.edu const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 672972Sgblack@eecs.umich.edu const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 682972Sgblack@eecs.umich.edu const int NumMiscRegs = NumControlRegs; 692131SN/A 702972Sgblack@eecs.umich.edu const int TotalNumRegs = NumIntRegs + NumFloatRegs + 712972Sgblack@eecs.umich.edu NumMiscRegs + 0/*NumInternalProcRegs*/; 722597SN/A 732972Sgblack@eecs.umich.edu const int TotalDataRegs = NumIntRegs + NumFloatRegs; 742597SN/A 752972Sgblack@eecs.umich.edu // Static instruction parameters 762972Sgblack@eecs.umich.edu const int MaxInstSrcRegs = 3; 772972Sgblack@eecs.umich.edu const int MaxInstDestRegs = 2; 782597SN/A 792972Sgblack@eecs.umich.edu // semantically meaningful register indices 802972Sgblack@eecs.umich.edu const int ZeroReg = 0; 812972Sgblack@eecs.umich.edu const int AssemblerReg = 1; 822972Sgblack@eecs.umich.edu const int ReturnValueReg = 2; 832972Sgblack@eecs.umich.edu const int ReturnValueReg1 = 2; 842972Sgblack@eecs.umich.edu const int ReturnValueReg2 = 3; 852972Sgblack@eecs.umich.edu const int ArgumentReg0 = 4; 862972Sgblack@eecs.umich.edu const int ArgumentReg1 = 5; 872972Sgblack@eecs.umich.edu const int ArgumentReg2 = 6; 882972Sgblack@eecs.umich.edu const int ArgumentReg3 = 7; 892972Sgblack@eecs.umich.edu const int KernelReg0 = 26; 902972Sgblack@eecs.umich.edu const int KernelReg1 = 27; 912972Sgblack@eecs.umich.edu const int GlobalPointerReg = 28; 922972Sgblack@eecs.umich.edu const int StackPointerReg = 29; 932972Sgblack@eecs.umich.edu const int FramePointerReg = 30; 942972Sgblack@eecs.umich.edu const int ReturnAddressReg = 31; 952597SN/A 962972Sgblack@eecs.umich.edu const int SyscallNumReg = ReturnValueReg1; 972972Sgblack@eecs.umich.edu const int SyscallPseudoReturnReg = ReturnValueReg1; 982972Sgblack@eecs.umich.edu const int SyscallSuccessReg = ArgumentReg3; 992131SN/A 1002972Sgblack@eecs.umich.edu const int LogVMPageSize = 13; // 8K bytes 1012972Sgblack@eecs.umich.edu const int VMPageSize = (1 << LogVMPageSize); 1022131SN/A 1032972Sgblack@eecs.umich.edu const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 1042131SN/A 1052972Sgblack@eecs.umich.edu const int MachineBytes = 4; 1062972Sgblack@eecs.umich.edu const int WordBytes = 4; 1072972Sgblack@eecs.umich.edu const int HalfwordBytes = 2; 1082972Sgblack@eecs.umich.edu const int ByteBytes = 1; 1092131SN/A 1102972Sgblack@eecs.umich.edu // These help enumerate all the registers for dependence tracking. 1112972Sgblack@eecs.umich.edu const int FP_Base_DepTag = 34; 1122972Sgblack@eecs.umich.edu const int Ctrl_Base_DepTag = 257; 1132131SN/A 1142972Sgblack@eecs.umich.edu const int ANNOTE_NONE = 0; 1152972Sgblack@eecs.umich.edu const uint32_t ITOUCH_ANNOTE = 0xffffffff; 1162131SN/A 1172023SN/A}; 1182023SN/A 1192447SN/Ausing namespace MipsISA; 1202447SN/A 1212028SN/A#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 122