isa_traits.hh revision 2665
12023SN/A/* 22023SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32023SN/A * All rights reserved. 42023SN/A * 52023SN/A * Redistribution and use in source and binary forms, with or without 62023SN/A * modification, are permitted provided that the following conditions are 72023SN/A * met: redistributions of source code must retain the above copyright 82023SN/A * notice, this list of conditions and the following disclaimer; 92023SN/A * redistributions in binary form must reproduce the above copyright 102023SN/A * notice, this list of conditions and the following disclaimer in the 112023SN/A * documentation and/or other materials provided with the distribution; 122023SN/A * neither the name of the copyright holders nor the names of its 132023SN/A * contributors may be used to endorse or promote products derived from 142023SN/A * this software without specific prior written permission. 152023SN/A * 162023SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172023SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182023SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192023SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202023SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212023SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222023SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232023SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242023SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252023SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262023SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292665Ssaidi@eecs.umich.edu * Korey Sewell 302023SN/A */ 312023SN/A 322028SN/A#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 332028SN/A#define __ARCH_MIPS_ISA_TRAITS_HH__ 342023SN/A 352597SN/A#include "arch/mips/constants.hh" 362597SN/A#include "arch/mips/types.hh" 372616SN/A#include "arch/mips/regfile/regfile.hh" 382572SN/A#include "arch/mips/faults.hh" 392597SN/A#include "arch/mips/utility.hh" 402023SN/A#include "base/misc.hh" 412131SN/A#include "config/full_system.hh" 422572SN/A#include "sim/byteswap.hh" 432023SN/A#include "sim/host.hh" 442131SN/A#include "sim/faults.hh" 452023SN/A 462239SN/A#include <vector> 472239SN/A 482023SN/Aclass FastCPU; 492028SN/Aclass FullCPU; 502028SN/Aclass Checkpoint; 512472SN/Aclass ExecContext; 522023SN/A 532239SN/Anamespace LittleEndianGuest {}; 542239SN/A 552028SN/A#define TARGET_MIPS 562023SN/A 572131SN/Aclass StaticInst; 582131SN/Aclass StaticInstPtr; 592023SN/A 602131SN/Anamespace MIPS34K { 612131SN/Aint DTB_ASN_ASN(uint64_t reg); 622131SN/Aint ITB_ASN_ASN(uint64_t reg); 632239SN/A}; 642023SN/A 652447SN/A#if !FULL_SYSTEM 662447SN/Aclass SyscallReturn { 672447SN/A public: 682447SN/A template <class T> 692447SN/A SyscallReturn(T v, bool s) 702447SN/A { 712495SN/A retval = (uint32_t)v; 722447SN/A success = s; 732447SN/A } 742447SN/A 752447SN/A template <class T> 762447SN/A SyscallReturn(T v) 772447SN/A { 782447SN/A success = (v >= 0); 792495SN/A retval = (uint32_t)v; 802447SN/A } 812447SN/A 822447SN/A ~SyscallReturn() {} 832447SN/A 842447SN/A SyscallReturn& operator=(const SyscallReturn& s) { 852447SN/A retval = s.retval; 862447SN/A success = s.success; 872447SN/A return *this; 882447SN/A } 892447SN/A 902447SN/A bool successful() { return success; } 912447SN/A uint64_t value() { return retval; } 922447SN/A 932447SN/A 942447SN/A private: 952447SN/A uint64_t retval; 962447SN/A bool success; 972447SN/A}; 982447SN/A#endif 992447SN/A 1002131SN/Anamespace MipsISA 1012023SN/A{ 1022525SN/A using namespace LittleEndianGuest; 1032525SN/A 1042597SN/A static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 1052538SN/A { 1062597SN/A if (return_value.successful()) { 1072597SN/A // no error 1082597SN/A regs->setIntReg(SyscallSuccessReg, 0); 1092597SN/A regs->setIntReg(ReturnValueReg1, return_value.value()); 1102597SN/A } else { 1112597SN/A // got an error, return details 1122597SN/A regs->setIntReg(SyscallSuccessReg, (IntReg) -1); 1132597SN/A regs->setIntReg(ReturnValueReg1, -return_value.value()); 1142538SN/A } 1152597SN/A } 1162023SN/A 1172447SN/A StaticInstPtr decodeInst(ExtMachInst); 1182023SN/A 1192447SN/A static inline ExtMachInst 1202447SN/A makeExtMI(MachInst inst, const uint64_t &pc) { 1212447SN/A#if FULL_SYSTEM 1222447SN/A ExtMachInst ext_inst = inst; 1232447SN/A if (pc && 0x1) 1242447SN/A return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 1252447SN/A else 1262447SN/A return ext_inst; 1272447SN/A#else 1282447SN/A return ExtMachInst(inst); 1292447SN/A#endif 1302447SN/A } 1312239SN/A 1322597SN/A /** 1332597SN/A * Function to insure ISA semantics about 0 registers. 1342597SN/A * @param xc The execution context. 1352597SN/A */ 1362597SN/A template <class XC> 1372597SN/A void zeroRegisters(XC *xc); 1382131SN/A 1392597SN/A const Addr MaxAddr = (Addr)-1; 1402131SN/A 1412597SN/A void copyRegs(ExecContext *src, ExecContext *dest); 1422131SN/A 1432605SN/A uint64_t fpConvert(double fp_val, ConvertType cvt_type); 1442616SN/A double roundFP(double val, int digits); 1452608SN/A double truncFP(double val); 1462616SN/A bool getFPConditionCode(uint32_t fcsr_reg, int cc); 1472616SN/A uint32_t makeCCVector(uint32_t fcsr, int num, bool val); 1482597SN/A 1492597SN/A // Machine operations 1502597SN/A 1512597SN/A void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 1522597SN/A int regnum); 1532597SN/A 1542597SN/A void restoreMachineReg(RegFile ®s, const AnyReg ®, 1552597SN/A int regnum); 1562597SN/A 1572597SN/A#if 0 1582597SN/A static void serializeSpecialRegs(const Serializable::Proxy &proxy, 1592597SN/A const RegFile ®s); 1602597SN/A 1612597SN/A static void unserializeSpecialRegs(const IniFile *db, 1622597SN/A const std::string &category, 1632597SN/A ConfigNode *node, 1642597SN/A RegFile ®s); 1652597SN/A#endif 1662131SN/A 1672131SN/A static inline Addr alignAddress(const Addr &addr, 1682131SN/A unsigned int nbytes) { 1692131SN/A return (addr & ~(nbytes - 1)); 1702131SN/A } 1712131SN/A 1722131SN/A // Instruction address compression hooks 1732131SN/A static inline Addr realPCToFetchPC(const Addr &addr) { 1742131SN/A return addr; 1752131SN/A } 1762131SN/A 1772131SN/A static inline Addr fetchPCToRealPC(const Addr &addr) { 1782131SN/A return addr; 1792131SN/A } 1802131SN/A 1812131SN/A // the size of "fetched" instructions (not necessarily the size 1822131SN/A // of real instructions for PISA) 1832131SN/A static inline size_t fetchInstSize() { 1842131SN/A return sizeof(MachInst); 1852131SN/A } 1862131SN/A 1872131SN/A static inline MachInst makeRegisterCopy(int dest, int src) { 1882131SN/A panic("makeRegisterCopy not implemented"); 1892131SN/A return 0; 1902131SN/A } 1912131SN/A 1922023SN/A}; 1932023SN/A 1942131SN/A#if FULL_SYSTEM 1952023SN/A 1962125SN/A#include "arch/mips/mips34k.hh" 1972597SN/A 1982023SN/A#endif 1992023SN/A 2002447SN/Ausing namespace MipsISA; 2012447SN/A 2022028SN/A#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 203