isa_traits.hh revision 2572
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 30#define __ARCH_MIPS_ISA_TRAITS_HH__ 31 32//#include "arch/mips/misc_regfile.hh" 33#include "arch/mips/faults.hh" 34#include "base/misc.hh" 35#include "config/full_system.hh" 36#include "sim/byteswap.hh" 37#include "sim/host.hh" 38#include "sim/faults.hh" 39 40#include <vector> 41 42class FastCPU; 43class FullCPU; 44class Checkpoint; 45class ExecContext; 46 47namespace LittleEndianGuest {}; 48 49#define TARGET_MIPS 50 51class StaticInst; 52class StaticInstPtr; 53 54namespace MIPS34K { 55int DTB_ASN_ASN(uint64_t reg); 56int ITB_ASN_ASN(uint64_t reg); 57}; 58 59#if !FULL_SYSTEM 60class SyscallReturn { 61 public: 62 template <class T> 63 SyscallReturn(T v, bool s) 64 { 65 retval = (uint32_t)v; 66 success = s; 67 } 68 69 template <class T> 70 SyscallReturn(T v) 71 { 72 success = (v >= 0); 73 retval = (uint32_t)v; 74 } 75 76 ~SyscallReturn() {} 77 78 SyscallReturn& operator=(const SyscallReturn& s) { 79 retval = s.retval; 80 success = s.success; 81 return *this; 82 } 83 84 bool successful() { return success; } 85 uint64_t value() { return retval; } 86 87 88 private: 89 uint64_t retval; 90 bool success; 91}; 92#endif 93 94namespace MipsISA 95{ 96 using namespace LittleEndianGuest; 97 98 typedef uint32_t MachInst; 99 typedef uint32_t MachInst; 100 typedef uint64_t ExtMachInst; 101 typedef uint8_t RegIndex; 102// typedef uint64_t Addr; 103 104 // Constants Related to the number of registers 105 106 const int NumIntArchRegs = 32; 107 const int NumPALShadowRegs = 8; 108 const int NumFloatArchRegs = 32; 109 // @todo: Figure out what this number really should be. 110 const int NumMiscArchRegs = 265; 111 112 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 113 const int NumFloatRegs = NumFloatArchRegs; 114 const int NumMiscRegs = NumMiscArchRegs; 115 116 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 117 NumMiscRegs + 0/*NumInternalProcRegs*/; 118 119 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 120 121 // Static instruction parameters 122 const int MaxInstSrcRegs = 3; 123 const int MaxInstDestRegs = 2; 124 125 // semantically meaningful register indices 126 const int ZeroReg = 0; 127 const int AssemblerReg = 1; 128 const int ReturnValueReg1 = 2; 129 const int ReturnValueReg2 = 3; 130 const int ArgumentReg0 = 4; 131 const int ArgumentReg1 = 5; 132 const int ArgumentReg2 = 6; 133 const int ArgumentReg3 = 7; 134 const int KernelReg0 = 26; 135 const int KernelReg1 = 27; 136 const int GlobalPointerReg = 28; 137 const int StackPointerReg = 29; 138 const int FramePointerReg = 30; 139 const int ReturnAddressReg = 31; 140 141 const int SyscallNumReg = ReturnValueReg1; 142 const int SyscallPseudoReturnReg = ReturnValueReg1; 143 const int SyscallSuccessReg = ArgumentReg3; 144 145 const int LogVMPageSize = 13; // 8K bytes 146 const int VMPageSize = (1 << LogVMPageSize); 147 148 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 149 150 const int MachineBytes = 4; 151 const int WordBytes = 4; 152 const int HalfwordBytes = 2; 153 const int ByteBytes = 1; 154 155 156 // These enumerate all the registers for dependence tracking. 157 enum DependenceTags { 158 // 0..31 are the integer regs 0..31 159 // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 160 FP_Base_DepTag = 32, 161 Ctrl_Base_DepTag = 64, 162 Fpcr_DepTag = 64, // floating point control register 163 Uniq_DepTag = 65, 164 IPR_Base_DepTag = 66, 165 MiscReg_DepTag = 67 166 }; 167 168 typedef uint64_t IntReg; 169 class IntRegFile 170 { 171 protected: 172 IntReg regs[NumIntRegs]; 173 174 public: 175 IntReg readReg(int intReg) 176 { 177 return regs[intReg]; 178 } 179 180 Fault setReg(int intReg, const IntReg &val) 181 { 182 regs[intReg] = val; 183 return NoFault; 184 } 185 186 void serialize(std::ostream &os); 187 188 void unserialize(Checkpoint *cp, const std::string §ion); 189 190 }; 191 192 typedef double FloatReg; 193 typedef uint64_t FloatRegBits; 194 195 const int SingleWidth = 32; 196 const int SingleBytes = SingleWidth / 4; 197 198 const int DoubleWidth = 64; 199 const int DoubleBytes = DoubleWidth / 4; 200 201 const int QuadWidth = 128; 202 const int QuadBytes = QuadWidth / 4; 203 204 const int FloatRegSize = SingleWidth / SingleBytes; 205 const int DoubleRegSize = FloatRegSize * 2; 206 207 class FloatRegFile 208 { 209 protected: 210 211 //Since the floating point registers overlap each other, 212 //A generic storage space is used. The float to be returned is 213 //pulled from the appropriate section of this region. 214 char regSpace[FloatRegSize * NumFloatRegs]; 215 216 public: 217 218 void clear() 219 { 220 bzero(regSpace, sizeof(regSpace)); 221 } 222 223 FloatReg readReg(int floatReg, int width) 224 { 225 //In each of these cases, we have to copy the value into a temporary 226 //variable. This is because we may otherwise try to access an 227 //unaligned portion of memory. 228 switch(width) 229 { 230 case SingleWidth: 231 float result32; 232 memcpy(&result32, regSpace + 4 * floatReg, FloatRegSize); 233 return htog(result32); 234 235 case DoubleWidth: 236 double result64; 237 memcpy(&result64, regSpace + 4 * floatReg, DoubleRegSize); 238 return htog(result64); 239 240 default: 241 panic("Attempted to read a %d bit floating point register!", width); 242 } 243 } 244 245 FloatRegBits readRegBits(int floatReg, int width) 246 { 247 //In each of these cases, we have to copy the value into a temporary 248 //variable. This is because we may otherwise try to access an 249 //unaligned portion of memory. 250 switch(width) 251 { 252 case SingleWidth: 253 uint32_t result32; 254 memcpy(&result32, regSpace + 4 * floatReg, FloatRegSize); 255 return htog(result32); 256 case DoubleWidth: 257 uint64_t result64; 258 memcpy(&result64, regSpace + 4 * floatReg, DoubleRegSize); 259 return htog(result64); 260 261 default: 262 panic("Attempted to read a %d bit floating point register!", width); 263 } 264 } 265 266 Fault setReg(int floatReg, const FloatReg &val, int width) 267 { 268 //In each of these cases, we have to copy the value into a temporary 269 //variable. This is because we may otherwise try to access an 270 //unaligned portion of memory. 271 switch(width) 272 { 273 case SingleWidth: 274 uint32_t result32; 275 result32 = gtoh((uint32_t)val); 276 memcpy(regSpace + 4 * floatReg, &result32, FloatRegSize); 277 break; 278 279 case DoubleWidth: 280 uint64_t result64; 281 result64 = gtoh((uint64_t)val); 282 memcpy(regSpace + 4 * floatReg, &result64, DoubleRegSize); 283 break; 284 285 286 default: 287 panic("Attempted to read a %d bit floating point register!", width); 288 } 289 return NoFault; 290 } 291 292 Fault setRegBits(int floatReg, const FloatRegBits &val, int width) 293 { 294 //In each of these cases, we have to copy the value into a temporary 295 //variable. This is because we may otherwise try to access an 296 //unaligned portion of memory. 297 switch(width) 298 { 299 case SingleWidth: 300 uint32_t result32; 301 result32 = gtoh((uint32_t)val); 302 memcpy(regSpace + 4 * floatReg, &result32, FloatRegSize); 303 break; 304 305 case DoubleWidth: 306 uint64_t result64; 307 result64 = gtoh((uint64_t)val); 308 memcpy(regSpace + 4 * floatReg, &result64, DoubleRegSize); 309 break; 310 311 default: 312 panic("Attempted to read a %d bit floating point register!", width); 313 } 314 return NoFault; 315 } 316 317 void serialize(std::ostream &os); 318 319 void unserialize(Checkpoint *cp, const std::string §ion); 320 }; 321 322 323 void copyRegs(ExecContext *src, ExecContext *dest); 324 325 // cop-0/cop-1 system control register file 326 typedef uint64_t MiscReg; 327//typedef MiscReg MiscRegFile[NumMiscRegs]; 328 class MiscRegFile { 329 330 protected: 331 uint64_t fpcr; // floating point condition codes 332 uint64_t uniq; // process-unique register 333 bool lock_flag; // lock flag for LL/SC 334 Addr lock_addr; // lock address for LL/SC 335 336 MiscReg miscRegFile[NumMiscRegs]; 337 338 public: 339 //These functions should be removed once the simplescalar cpu model 340 //has been replaced. 341 int getInstAsid(); 342 int getDataAsid(); 343 344 void copyMiscRegs(ExecContext *xc); 345 346 MiscReg readReg(int misc_reg) 347 { return miscRegFile[misc_reg]; } 348 349 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc) 350 { return miscRegFile[misc_reg];} 351 352 Fault setReg(int misc_reg, const MiscReg &val) 353 { miscRegFile[misc_reg] = val; return NoFault; } 354 355 Fault setRegWithEffect(int misc_reg, const MiscReg &val, 356 ExecContext *xc) 357 { miscRegFile[misc_reg] = val; return NoFault; } 358 359#if FULL_SYSTEM 360 void clearIprs() { } 361 362 protected: 363 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 364 365 private: 366 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { } 367 368 Fault setIpr(int idx, uint64_t val, ExecContext *xc) { } 369#endif 370 friend class RegFile; 371 }; 372 373 enum MiscRegTags { 374 //Coprocessor 0 Registers 375 //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 376 //(Register Number-Register Select) Summary of Register 377 //------------------------------------------------------ 378 Index = 0, //0-0 Index into the TLB array 379 380 MVPControl = 1, //0-1 Per-processor register containing global 381 //MIPS� MT configuration data 382 383 MVPConf0 = 2, //0-2 Per-processor register containing global 384 //MIPS� MT configuration data 385 386 MVPConf1 = 3, //0-3 Per-processor register containing global 387 //MIPS� MT configuration data 388 389 Random = 8, //1-0 Randomly generated index into the TLB array 390 391 VPEControl = 9, //1-1 Per-VPE register containing relatively volatile 392 //thread configuration data 393 394 VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration 395 //information 396 397 398 VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration 399 //information 400 401 YQMask = 12, //Per-VPE register defining which YIELD 402 //qualifier bits may be used without generating 403 //an exception 404 405 VPESchedule = 13, 406 VPEScheFBack = 14, 407 VPEOpt = 15, 408 EntryLo0 = 16, // Bank 3: 16 - 23 409 TCStatus = 17, 410 TCBind = 18, 411 TCRestart = 19, 412 TCHalt = 20, 413 TCContext = 21, 414 TCSchedule = 22, 415 TCScheFBack = 23, 416 417 EntryLo1 = 24,// Bank 4: 24 - 31 418 419 Context = 32, // Bank 5: 32 - 39 420 ContextConfig = 33, 421 422 //PageMask = 40, //Bank 6: 40 - 47 423 PageGrain = 41, 424 425 Wired = 48, //Bank 7:48 - 55 426 SRSConf0 = 49, 427 SRSConf1 = 50, 428 SRSConf2 = 51, 429 SRSConf3 = 52, 430 SRSConf4 = 53, 431 BadVAddr = 54, 432 433 HWRena = 56,//Bank 8:56 - 63 434 435 Count = 64, //Bank 9:64 - 71 436 437 EntryHi = 72,//Bank 10:72 - 79 438 439 Compare = 80,//Bank 11:80 - 87 440 441 Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control 442 IntCtl = 89, //12-1 Interrupt system status and control 443 SRSCtl = 90, //12-2 Shadow register set status and control 444 SRSMap = 91, //12-3 Shadow set IPL mapping 445 446 Cause = 97,//97-104 //13-0 Cause of last general exception 447 448 EPC = 105,//105-112 //14-0 Program counter at last exception 449 450 PRId = 113,//113-120, //15-0 Processor identification and revision 451 EBase = 114, //15-1 Exception vector base register 452 453 Config = 121,//Bank 16: 121-128 454 Config1 = 122, 455 Config2 = 123, 456 Config3 = 124, 457 Config6 = 127, 458 Config7 = 128, 459 460 461 LLAddr = 129,//Bank 17: 129-136 462 463 WatchLo0 = 137,//Bank 18: 137-144 464 WatchLo1 = 138, 465 WatchLo2 = 139, 466 WatchLo3 = 140, 467 WatchLo4 = 141, 468 WatchLo5 = 142, 469 WatchLo6 = 143, 470 WatchLo7 = 144, 471 472 WatchHi0 = 145,//Bank 19: 145-152 473 WatchHi1 = 146, 474 WatchHi2 = 147, 475 WatchHi3 = 148, 476 WatchHi4 = 149, 477 WatchHi5 = 150, 478 WatchHi6 = 151, 479 WatchHi7 = 152, 480 481 XCContext64 = 153,//Bank 20: 153-160 482 483 //Bank 21: 161-168 484 485 //Bank 22: 169-176 486 487 Debug = 177, //Bank 23: 177-184 488 TraceControl1 = 178, 489 TraceControl2 = 179, 490 UserTraceData = 180, 491 TraceBPC = 181, 492 493 DEPC = 185,//Bank 24: 185-192 494 495 PerfCnt0 = 193,//Bank 25: 193 - 200 496 PerfCnt1 = 194, 497 PerfCnt2 = 195, 498 PerfCnt3 = 196, 499 PerfCnt4 = 197, 500 PerfCnt5 = 198, 501 PerfCnt6 = 199, 502 PerfCnt7 = 200, 503 504 ErrCtl = 201, //Bank 26: 201 - 208 505 506 CacheErr0 = 209, //Bank 27: 209 - 216 507 CacheErr1 = 210, 508 CacheErr2 = 211, 509 CacheErr3 = 212, 510 511 TagLo0 = 217,//Bank 28: 217 - 224 512 DataLo1 = 218, 513 TagLo2 = 219, 514 DataLo3 = 220, 515 TagLo4 = 221, 516 DataLo5 = 222, 517 TagLo6 = 223, 518 DataLo7 = 234, 519 520 TagHi0 = 233,//Bank 29: 233 - 240 521 DataHi1 = 234, 522 TagHi2 = 235, 523 DataHi3 = 236, 524 TagHi4 = 237, 525 DataHi5 = 238, 526 TagHi6 = 239, 527 DataHi7 = 240, 528 529 530 ErrorEPC = 249,//Bank 30: 241 - 248 531 532 DESAVE = 257,//Bank 31: 249-256 533 534 //More Misc. Regs 535 Hi, 536 Lo, 537 FIR, 538 FCSR, 539 FPCR, 540 541 //Alpha Regs, but here now, for 542 //compiling sake 543 UNIQ, 544 LockAddr, 545 LockFlag 546 }; 547 548extern const Addr PageShift; 549extern const Addr PageBytes; 550extern const Addr PageMask; 551extern const Addr PageOffset; 552 553#if FULL_SYSTEM 554 555 typedef uint64_t InternalProcReg; 556 557#include "arch/mips/isa_fullsys_traits.hh" 558 559#else 560 enum { 561 NumInternalProcRegs = 0 562 }; 563#endif 564 565 typedef union { 566 IntReg intreg; 567 FloatReg fpreg; 568 MiscReg ctrlreg; 569 } AnyReg; 570 571 class RegFile { 572 protected: 573 IntRegFile intRegFile; // (signed) integer register file 574 FloatRegFile floatRegFile; // floating point register file 575 MiscRegFile miscRegFile; // control register file 576 577 public: 578 579 void clear() 580 { 581 bzero(&intRegFile, sizeof(intRegFile)); 582 bzero(&floatRegFile, sizeof(floatRegFile)); 583 bzero(&miscRegFile, sizeof(miscRegFile)); 584 } 585 586 MiscReg readMiscReg(int miscReg) 587 { 588 return miscRegFile.readReg(miscReg); 589 } 590 591 MiscReg readMiscRegWithEffect(int miscReg, 592 Fault &fault, ExecContext *xc) 593 { 594 fault = NoFault; 595 return miscRegFile.readRegWithEffect(miscReg, fault, xc); 596 } 597 598 Fault setMiscReg(int miscReg, const MiscReg &val) 599 { 600 return miscRegFile.setReg(miscReg, val); 601 } 602 603 Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, 604 ExecContext * xc) 605 { 606 return miscRegFile.setRegWithEffect(miscReg, val, xc); 607 } 608 609 610 FloatReg readFloatReg(int floatReg) 611 { 612 return floatRegFile.readReg(floatReg,SingleWidth); 613 } 614 615 FloatReg readFloatReg(int floatReg, int width) 616 { 617 return floatRegFile.readReg(floatReg,width); 618 } 619 620 FloatRegBits readFloatRegBits(int floatReg) 621 { 622 return floatRegFile.readRegBits(floatReg,SingleWidth); 623 } 624 625 FloatRegBits readFloatRegBits(int floatReg, int width) 626 { 627 return floatRegFile.readRegBits(floatReg,width); 628 } 629 630 Fault setFloatReg(int floatReg, const FloatReg &val) 631 { 632 return floatRegFile.setReg(floatReg, val, SingleWidth); 633 } 634 635 Fault setFloatReg(int floatReg, const FloatReg &val, int width) 636 { 637 return floatRegFile.setReg(floatReg, val, width); 638 } 639 640 Fault setFloatRegBits(int floatReg, const FloatRegBits &val) 641 { 642 return floatRegFile.setRegBits(floatReg, val, SingleWidth); 643 } 644 645 Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) 646 { 647 return floatRegFile.setRegBits(floatReg, val, width); 648 } 649 650 IntReg readIntReg(int intReg) 651 { 652 return intRegFile.readReg(intReg); 653 } 654 655 Fault setIntReg(int intReg, const IntReg &val) 656 { 657 return intRegFile.setReg(intReg, val); 658 } 659 protected: 660 661 Addr pc; // program counter 662 Addr npc; // next-cycle program counter 663 Addr nnpc; // next-next-cycle program counter 664 // used to implement branch delay slot 665 // not real register 666 public: 667 Addr readPC() 668 { 669 return pc; 670 } 671 672 void setPC(Addr val) 673 { 674 pc = val; 675 } 676 677 Addr readNextPC() 678 { 679 return npc; 680 } 681 682 void setNextPC(Addr val) 683 { 684 npc = val; 685 } 686 687 Addr readNextNPC() 688 { 689 return nnpc; 690 } 691 692 void setNextNPC(Addr val) 693 { 694 nnpc = val; 695 } 696 697 MiscReg hi; // MIPS HI Register 698 MiscReg lo; // MIPS LO Register 699 700 701#if FULL_SYSTEM 702 IntReg palregs[NumIntRegs]; // PAL shadow registers 703 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 704 int intrflag; // interrupt flag 705 bool pal_shadow; // using pal_shadow registers 706 inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } 707 inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } 708#endif // FULL_SYSTEM 709 710 //void initCP0Regs(); 711 void serialize(std::ostream &os); 712 void unserialize(Checkpoint *cp, const std::string §ion); 713 714 void createCP0Regs(); 715 void coldReset(); 716 717 typedef int ContextParam; 718 typedef int ContextVal; 719 720 void changeContext(ContextParam param, ContextVal val) 721 { 722 } 723 }; 724 725 StaticInstPtr decodeInst(ExtMachInst); 726 727 // return a no-op instruction... used for instruction fetch faults 728 extern const MachInst NoopMachInst; 729 730 enum annotes { 731 ANNOTE_NONE = 0, 732 // An impossible number for instruction annotations 733 ITOUCH_ANNOTE = 0xffffffff, 734 }; 735 736//void getMiscRegIdx(int reg_name,int &idx, int &sel); 737 738 static inline ExtMachInst 739 makeExtMI(MachInst inst, const uint64_t &pc) { 740#if FULL_SYSTEM 741 ExtMachInst ext_inst = inst; 742 if (pc && 0x1) 743 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 744 else 745 return ext_inst; 746#else 747 return ExtMachInst(inst); 748#endif 749 } 750 751 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 752 panic("register classification not implemented"); 753 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 754 } 755 756 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 757 panic("register classification not implemented"); 758 return (reg >= 9 && reg <= 15); 759 } 760 761 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 762 panic("register classification not implemented"); 763 return false; 764 } 765 766 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 767 panic("register classification not implemented"); 768 return false; 769 } 770 771 static inline Addr alignAddress(const Addr &addr, 772 unsigned int nbytes) { 773 return (addr & ~(nbytes - 1)); 774 } 775 776 // Instruction address compression hooks 777 static inline Addr realPCToFetchPC(const Addr &addr) { 778 return addr; 779 } 780 781 static inline Addr fetchPCToRealPC(const Addr &addr) { 782 return addr; 783 } 784 785 // the size of "fetched" instructions (not necessarily the size 786 // of real instructions for PISA) 787 static inline size_t fetchInstSize() { 788 return sizeof(MachInst); 789 } 790 791 static inline MachInst makeRegisterCopy(int dest, int src) { 792 panic("makeRegisterCopy not implemented"); 793 return 0; 794 } 795 796 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 797 { 798 if (return_value.successful()) { 799 // no error 800 regs->setIntReg(SyscallSuccessReg, 0); 801 regs->setIntReg(ReturnValueReg1, return_value.value()); 802 } else { 803 // got an error, return details 804 regs->setIntReg(SyscallSuccessReg, (IntReg) -1); 805 regs->setIntReg(ReturnValueReg1, -return_value.value()); 806 } 807 } 808 809 // Machine operations 810 811 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 812 int regnum); 813 814 void restoreMachineReg(RegFile ®s, const AnyReg ®, 815 int regnum); 816 817#if 0 818 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 819 const RegFile ®s); 820 821 static void unserializeSpecialRegs(const IniFile *db, 822 const std::string &category, 823 ConfigNode *node, 824 RegFile ®s); 825#endif 826 827 /** 828 * Function to insure ISA semantics about 0 registers. 829 * @param xc The execution context. 830 */ 831 template <class XC> 832 void zeroRegisters(XC *xc); 833 834 const Addr MaxAddr = (Addr)-1; 835}; 836 837#if FULL_SYSTEM 838//typedef TheISA::InternalProcReg InternalProcReg; 839//const int NumInternalProcRegs = TheISA::NumInternalProcRegs; 840//const int NumInterruptLevels = TheISA::NumInterruptLevels; 841 842#include "arch/mips/mips34k.hh" 843#endif 844 845using namespace MipsISA; 846 847#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 848