isa_traits.hh revision 2538
16911SBrad.Beckmann@amd.com/* 26911SBrad.Beckmann@amd.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 36911SBrad.Beckmann@amd.com * All rights reserved. 46911SBrad.Beckmann@amd.com * 56911SBrad.Beckmann@amd.com * Redistribution and use in source and binary forms, with or without 66911SBrad.Beckmann@amd.com * modification, are permitted provided that the following conditions are 76911SBrad.Beckmann@amd.com * met: redistributions of source code must retain the above copyright 86911SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer; 96911SBrad.Beckmann@amd.com * redistributions in binary form must reproduce the above copyright 106911SBrad.Beckmann@amd.com * notice, this list of conditions and the following disclaimer in the 116911SBrad.Beckmann@amd.com * documentation and/or other materials provided with the distribution; 126911SBrad.Beckmann@amd.com * neither the name of the copyright holders nor the names of its 136911SBrad.Beckmann@amd.com * contributors may be used to endorse or promote products derived from 146911SBrad.Beckmann@amd.com * this software without specific prior written permission. 156911SBrad.Beckmann@amd.com * 166911SBrad.Beckmann@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176911SBrad.Beckmann@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186911SBrad.Beckmann@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196911SBrad.Beckmann@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206911SBrad.Beckmann@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216911SBrad.Beckmann@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226911SBrad.Beckmann@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236911SBrad.Beckmann@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246911SBrad.Beckmann@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256911SBrad.Beckmann@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266911SBrad.Beckmann@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276911SBrad.Beckmann@amd.com */ 286911SBrad.Beckmann@amd.com 296911SBrad.Beckmann@amd.com#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 306911SBrad.Beckmann@amd.com#define __ARCH_MIPS_ISA_TRAITS_HH__ 316911SBrad.Beckmann@amd.com 326911SBrad.Beckmann@amd.com//#include "arch/mips/misc_regfile.hh" 336911SBrad.Beckmann@amd.com#include "base/misc.hh" 349100SBrad.Beckmann@amd.com#include "config/full_system.hh" 356911SBrad.Beckmann@amd.com#include "sim/host.hh" 366911SBrad.Beckmann@amd.com#include "sim/faults.hh" 376911SBrad.Beckmann@amd.com 386911SBrad.Beckmann@amd.com#include <vector> 396911SBrad.Beckmann@amd.com 406911SBrad.Beckmann@amd.comclass FastCPU; 416911SBrad.Beckmann@amd.comclass FullCPU; 426911SBrad.Beckmann@amd.comclass Checkpoint; 436911SBrad.Beckmann@amd.comclass ExecContext; 446911SBrad.Beckmann@amd.com 456911SBrad.Beckmann@amd.comnamespace LittleEndianGuest {}; 466911SBrad.Beckmann@amd.com 476911SBrad.Beckmann@amd.com#define TARGET_MIPS 487538SBrad.Beckmann@amd.com 497538SBrad.Beckmann@amd.comclass StaticInst; 507538SBrad.Beckmann@amd.comclass StaticInstPtr; 518929Snilay@cs.wisc.edu 528436SBrad.Beckmann@amd.comnamespace MIPS34K { 536911SBrad.Beckmann@amd.comint DTB_ASN_ASN(uint64_t reg); 546911SBrad.Beckmann@amd.comint ITB_ASN_ASN(uint64_t reg); 556911SBrad.Beckmann@amd.com}; 566911SBrad.Beckmann@amd.com 576911SBrad.Beckmann@amd.com#if !FULL_SYSTEM 586911SBrad.Beckmann@amd.comclass SyscallReturn { 596911SBrad.Beckmann@amd.com public: 606911SBrad.Beckmann@amd.com template <class T> 616911SBrad.Beckmann@amd.com SyscallReturn(T v, bool s) 626911SBrad.Beckmann@amd.com { 636911SBrad.Beckmann@amd.com retval = (uint32_t)v; 646911SBrad.Beckmann@amd.com success = s; 656911SBrad.Beckmann@amd.com } 666911SBrad.Beckmann@amd.com 676911SBrad.Beckmann@amd.com template <class T> 686911SBrad.Beckmann@amd.com SyscallReturn(T v) 696911SBrad.Beckmann@amd.com { 706911SBrad.Beckmann@amd.com success = (v >= 0); 716911SBrad.Beckmann@amd.com retval = (uint32_t)v; 728180SBrad.Beckmann@amd.com } 738180SBrad.Beckmann@amd.com 748257SBrad.Beckmann@amd.com ~SyscallReturn() {} 758257SBrad.Beckmann@amd.com 766911SBrad.Beckmann@amd.com SyscallReturn& operator=(const SyscallReturn& s) { 776911SBrad.Beckmann@amd.com retval = s.retval; 786911SBrad.Beckmann@amd.com success = s.success; 796911SBrad.Beckmann@amd.com return *this; 806911SBrad.Beckmann@amd.com } 816911SBrad.Beckmann@amd.com 828180SBrad.Beckmann@amd.com bool successful() { return success; } 838180SBrad.Beckmann@amd.com uint64_t value() { return retval; } 846911SBrad.Beckmann@amd.com 858180SBrad.Beckmann@amd.com 868180SBrad.Beckmann@amd.com private: 876911SBrad.Beckmann@amd.com uint64_t retval; 888322Ssteve.reinhardt@amd.com bool success; 898322Ssteve.reinhardt@amd.com}; 908322Ssteve.reinhardt@amd.com#endif 918322Ssteve.reinhardt@amd.com 928436SBrad.Beckmann@amd.comnamespace MipsISA 938717Snilay@cs.wisc.edu{ 948717Snilay@cs.wisc.edu using namespace LittleEndianGuest; 958436SBrad.Beckmann@amd.com 968322Ssteve.reinhardt@amd.com typedef uint32_t MachInst; 977015SBrad.Beckmann@amd.com typedef uint32_t MachInst; 987015SBrad.Beckmann@amd.com typedef uint64_t ExtMachInst; 996911SBrad.Beckmann@amd.com typedef uint8_t RegIndex; 1008436SBrad.Beckmann@amd.com// typedef uint64_t Addr; 1016911SBrad.Beckmann@amd.com 1028322Ssteve.reinhardt@amd.com // Constants Related to the number of registers 1038322Ssteve.reinhardt@amd.com 1046911SBrad.Beckmann@amd.com const int NumIntArchRegs = 32; 1058845Sandreas.hansson@arm.com const int NumPALShadowRegs = 8; 1066911SBrad.Beckmann@amd.com const int NumFloatArchRegs = 32; 1077541SBrad.Beckmann@amd.com // @todo: Figure out what this number really should be. 1086911SBrad.Beckmann@amd.com const int NumMiscArchRegs = 32; 1096911SBrad.Beckmann@amd.com 1106911SBrad.Beckmann@amd.com const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; 1116911SBrad.Beckmann@amd.com const int NumFloatRegs = NumFloatArchRegs; 1126911SBrad.Beckmann@amd.com const int NumMiscRegs = NumMiscArchRegs; 1136911SBrad.Beckmann@amd.com 1148257SBrad.Beckmann@amd.com const int TotalNumRegs = NumIntRegs + NumFloatRegs + 1158257SBrad.Beckmann@amd.com NumMiscRegs + 0/*NumInternalProcRegs*/; 1168180SBrad.Beckmann@amd.com 1178180SBrad.Beckmann@amd.com const int TotalDataRegs = NumIntRegs + NumFloatRegs; 1186911SBrad.Beckmann@amd.com 1196911SBrad.Beckmann@amd.com // Static instruction parameters 1206911SBrad.Beckmann@amd.com const int MaxInstSrcRegs = 3; 1216911SBrad.Beckmann@amd.com const int MaxInstDestRegs = 2; 1226911SBrad.Beckmann@amd.com 1238180SBrad.Beckmann@amd.com // semantically meaningful register indices 1248180SBrad.Beckmann@amd.com const int ZeroReg = 0; 1256911SBrad.Beckmann@amd.com const int AssemblerReg = 1; 1266911SBrad.Beckmann@amd.com const int ReturnValueReg1 = 2; 1278257SBrad.Beckmann@amd.com const int ReturnValueReg2 = 3; 1288436SBrad.Beckmann@amd.com const int ArgumentReg0 = 4; 1298436SBrad.Beckmann@amd.com const int ArgumentReg1 = 5; 1306911SBrad.Beckmann@amd.com const int ArgumentReg2 = 6; 1317541SBrad.Beckmann@amd.com const int ArgumentReg3 = 7; 1326911SBrad.Beckmann@amd.com const int KernelReg0 = 26; 1338257SBrad.Beckmann@amd.com const int KernelReg1 = 27; 1348257SBrad.Beckmann@amd.com const int GlobalPointerReg = 28; 1359232Sandreas.hansson@arm.com const int StackPointerReg = 29; 1369232Sandreas.hansson@arm.com const int FramePointerReg = 30; 1379232Sandreas.hansson@arm.com const int ReturnAddressReg = 31; 1386911SBrad.Beckmann@amd.com 1396911SBrad.Beckmann@amd.com const int SyscallNumReg = ReturnValueReg1; 1406911SBrad.Beckmann@amd.com const int SyscallPseudoReturnReg = ReturnValueReg1; 1416911SBrad.Beckmann@amd.com const int SyscallSuccessReg = ArgumentReg3; 1426911SBrad.Beckmann@amd.com 1436911SBrad.Beckmann@amd.com const int LogVMPageSize = 13; // 8K bytes 1446911SBrad.Beckmann@amd.com const int VMPageSize = (1 << LogVMPageSize); 1459154Spower.jg@gmail.com 1469154Spower.jg@gmail.com const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 1476911SBrad.Beckmann@amd.com 1486911SBrad.Beckmann@amd.com const int MachineBytes = 4; 1496911SBrad.Beckmann@amd.com const int WordBytes = 4; 1506911SBrad.Beckmann@amd.com const int HalfwordBytes = 2; 1516911SBrad.Beckmann@amd.com const int ByteBytes = 1; 1528257SBrad.Beckmann@amd.com 1536911SBrad.Beckmann@amd.com 1546911SBrad.Beckmann@amd.com // These enumerate all the registers for dependence tracking. 1558436SBrad.Beckmann@amd.com enum DependenceTags { 1568436SBrad.Beckmann@amd.com // 0..31 are the integer regs 0..31 1578436SBrad.Beckmann@amd.com // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) 1586911SBrad.Beckmann@amd.com FP_Base_DepTag = 32, 1597541SBrad.Beckmann@amd.com Ctrl_Base_DepTag = 64, 1606911SBrad.Beckmann@amd.com Fpcr_DepTag = 64, // floating point control register 1616911SBrad.Beckmann@amd.com Uniq_DepTag = 65, 1628257SBrad.Beckmann@amd.com IPR_Base_DepTag = 66, 1638257SBrad.Beckmann@amd.com MiscReg_DepTag = 67 1648929Snilay@cs.wisc.edu }; 1656911SBrad.Beckmann@amd.com 1666911SBrad.Beckmann@amd.com typedef uint64_t IntReg; 1676911SBrad.Beckmann@amd.com 1686911SBrad.Beckmann@amd.com class IntRegFile 1698477Snilay@cs.wisc.edu { 1706911SBrad.Beckmann@amd.com protected: 1716911SBrad.Beckmann@amd.com IntReg regs[NumIntRegs]; 1728257SBrad.Beckmann@amd.com 1738477Snilay@cs.wisc.edu public: 1748477Snilay@cs.wisc.edu IntReg readReg(int intReg) 1756911SBrad.Beckmann@amd.com { 1767541SBrad.Beckmann@amd.com return regs[intReg]; 1778929Snilay@cs.wisc.edu } 1786911SBrad.Beckmann@amd.com 1798257SBrad.Beckmann@amd.com Fault setReg(int intReg, const IntReg &val) 1808257SBrad.Beckmann@amd.com { 1816911SBrad.Beckmann@amd.com regs[intReg] = val; 1826911SBrad.Beckmann@amd.com return NoFault; 1836911SBrad.Beckmann@amd.com } 1846911SBrad.Beckmann@amd.com 1856911SBrad.Beckmann@amd.com void serialize(std::ostream &os); 1869100SBrad.Beckmann@amd.com 1879100SBrad.Beckmann@amd.com void unserialize(Checkpoint *cp, const std::string §ion); 1889100SBrad.Beckmann@amd.com 189 }; 190 191/* floating point register file entry type 192 typedef union { 193 uint64_t q; 194 double d; 195 } FloatReg;*/ 196 197 typedef double FloatReg; 198 typedef uint64_t FloatRegBits; 199 200/*typedef union { 201 uint64_t q[NumFloatRegs]; // integer qword view 202 double d[NumFloatRegs]; // double-precision floating point view 203 } FloatRegFile;*/ 204 205 class FloatRegFile 206 { 207 protected: 208 209 FloatRegBits q[NumFloatRegs]; // integer qword view 210 double d[NumFloatRegs]; // double-precision floating point view 211 212 public: 213 214 FloatReg readReg(int floatReg) 215 { 216 return d[floatReg]; 217 } 218 219 FloatReg readReg(int floatReg, int width) 220 { 221 return readReg(floatReg); 222 } 223 224 FloatRegBits readRegBits(int floatReg) 225 { 226 return q[floatReg]; 227 } 228 229 FloatRegBits readRegBits(int floatReg, int width) 230 { 231 return readRegBits(floatReg); 232 } 233 234 Fault setReg(int floatReg, const FloatReg &val) 235 { 236 d[floatReg] = val; 237 return NoFault; 238 } 239 240 Fault setReg(int floatReg, const FloatReg &val, int width) 241 { 242 return setReg(floatReg, val); 243 } 244 245 Fault setRegBits(int floatReg, const FloatRegBits &val) 246 { 247 q[floatReg] = val; 248 return NoFault; 249 } 250 251 Fault setRegBits(int floatReg, const FloatRegBits &val, int width) 252 { 253 return setRegBits(floatReg, val); 254 } 255 256 void serialize(std::ostream &os); 257 258 void unserialize(Checkpoint *cp, const std::string §ion); 259 260 }; 261 262 void copyRegs(ExecContext *src, ExecContext *dest); 263 264 // cop-0/cop-1 system control register file 265 typedef uint64_t MiscReg; 266//typedef MiscReg MiscRegFile[NumMiscRegs]; 267 class MiscRegFile { 268 269 protected: 270 uint64_t fpcr; // floating point condition codes 271 uint64_t uniq; // process-unique register 272 bool lock_flag; // lock flag for LL/SC 273 Addr lock_addr; // lock address for LL/SC 274 275 MiscReg miscRegFile[NumMiscRegs]; 276 277 public: 278 //These functions should be removed once the simplescalar cpu model 279 //has been replaced. 280 int getInstAsid(); 281 int getDataAsid(); 282 283 void copyMiscRegs(ExecContext *xc); 284 285 MiscReg readReg(int misc_reg) 286 { return miscRegFile[misc_reg]; } 287 288 MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc) 289 { return miscRegFile[misc_reg];} 290 291 Fault setReg(int misc_reg, const MiscReg &val) 292 { miscRegFile[misc_reg] = val; return NoFault; } 293 294 Fault setRegWithEffect(int misc_reg, const MiscReg &val, 295 ExecContext *xc) 296 { miscRegFile[misc_reg] = val; return NoFault; } 297 298#if FULL_SYSTEM 299 void clearIprs() { } 300 301 protected: 302 InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs 303 304 private: 305 MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { } 306 307 Fault setIpr(int idx, uint64_t val, ExecContext *xc) { } 308#endif 309 friend class RegFile; 310 }; 311 312 enum MiscRegTags { 313 //Coprocessor 0 Registers 314 //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 315 //(Register Number-Register Select) Summary of Register 316 //------------------------------------------------------ 317 Index = 0, //0-0 Index into the TLB array 318 319 MVPControl = 1, //0-1 Per-processor register containing global 320 //MIPS� MT configuration data 321 322 MVPConf0 = 2, //0-2 Per-processor register containing global 323 //MIPS� MT configuration data 324 325 MVPConf1 = 3, //0-3 Per-processor register containing global 326 //MIPS� MT configuration data 327 328 Random = 8, //1-0 Randomly generated index into the TLB array 329 330 VPEControl = 9, //1-1 Per-VPE register containing relatively volatile 331 //thread configuration data 332 333 VPEConf0 = 10, //1-2 Per-VPE multi-thread configuration 334 //information 335 336 337 VPEConf1 = 11, //1-2 Per-VPE multi-thread configuration 338 //information 339 340 YQMask = 12, //Per-VPE register defining which YIELD 341 //qualifier bits may be used without generating 342 //an exception 343 344 VPESchedule = 13, 345 VPEScheFBack = 14, 346 VPEOpt = 15, 347 EntryLo0 = 16, // Bank 3: 16 - 23 348 TCStatus = 17, 349 TCBind = 18, 350 TCRestart = 19, 351 TCHalt = 20, 352 TCContext = 21, 353 TCSchedule = 22, 354 TCScheFBack = 23, 355 356 EntryLo1 = 24,// Bank 4: 24 - 31 357 358 Context = 32, // Bank 5: 32 - 39 359 ContextConfig = 33, 360 361 //PageMask = 40, //Bank 6: 40 - 47 362 PageGrain = 41, 363 364 Wired = 48, //Bank 7:48 - 55 365 SRSConf0 = 49, 366 SRSConf1 = 50, 367 SRSConf2 = 51, 368 SRSConf3 = 52, 369 SRSConf4 = 53, 370 BadVAddr = 54, 371 372 HWRena = 56,//Bank 8:56 - 63 373 374 Count = 64, //Bank 9:64 - 71 375 376 EntryHi = 72,//Bank 10:72 - 79 377 378 Compare = 80,//Bank 11:80 - 87 379 380 Status = 88,//Bank 12:88 - 96 //12-0 Processor status and control 381 IntCtl = 89, //12-1 Interrupt system status and control 382 SRSCtl = 90, //12-2 Shadow register set status and control 383 SRSMap = 91, //12-3 Shadow set IPL mapping 384 385 Cause = 97,//97-104 //13-0 Cause of last general exception 386 387 EPC = 105,//105-112 //14-0 Program counter at last exception 388 389 PRId = 113,//113-120, //15-0 Processor identification and revision 390 EBase = 114, //15-1 Exception vector base register 391 392 Config = 121,//Bank 16: 121-128 393 Config1 = 122, 394 Config2 = 123, 395 Config3 = 124, 396 Config6 = 127, 397 Config7 = 128, 398 399 400 LLAddr = 129,//Bank 17: 129-136 401 402 WatchLo0 = 137,//Bank 18: 137-144 403 WatchLo1 = 138, 404 WatchLo2 = 139, 405 WatchLo3 = 140, 406 WatchLo4 = 141, 407 WatchLo5 = 142, 408 WatchLo6 = 143, 409 WatchLo7 = 144, 410 411 WatchHi0 = 145,//Bank 19: 145-152 412 WatchHi1 = 146, 413 WatchHi2 = 147, 414 WatchHi3 = 148, 415 WatchHi4 = 149, 416 WatchHi5 = 150, 417 WatchHi6 = 151, 418 WatchHi7 = 152, 419 420 XCContext64 = 153,//Bank 20: 153-160 421 422 //Bank 21: 161-168 423 424 //Bank 22: 169-176 425 426 Debug = 177, //Bank 23: 177-184 427 TraceControl1 = 178, 428 TraceControl2 = 179, 429 UserTraceData = 180, 430 TraceBPC = 181, 431 432 DEPC = 185,//Bank 24: 185-192 433 434 PerfCnt0 = 193,//Bank 25: 193 - 200 435 PerfCnt1 = 194, 436 PerfCnt2 = 195, 437 PerfCnt3 = 196, 438 PerfCnt4 = 197, 439 PerfCnt5 = 198, 440 PerfCnt6 = 199, 441 PerfCnt7 = 200, 442 443 ErrCtl = 201, //Bank 26: 201 - 208 444 445 CacheErr0 = 209, //Bank 27: 209 - 216 446 CacheErr1 = 210, 447 CacheErr2 = 211, 448 CacheErr3 = 212, 449 450 TagLo0 = 217,//Bank 28: 217 - 224 451 DataLo1 = 218, 452 TagLo2 = 219, 453 DataLo3 = 220, 454 TagLo4 = 221, 455 DataLo5 = 222, 456 TagLo6 = 223, 457 DataLo7 = 234, 458 459 TagHi0 = 233,//Bank 29: 233 - 240 460 DataHi1 = 234, 461 TagHi2 = 235, 462 DataHi3 = 236, 463 TagHi4 = 237, 464 DataHi5 = 238, 465 TagHi6 = 239, 466 DataHi7 = 240, 467 468 469 ErrorEPC = 249,//Bank 30: 241 - 248 470 471 DESAVE = 257,//Bank 31: 249-256 472 473 //More Misc. Regs 474 Hi, 475 Lo, 476 FCSR, 477 FPCR, 478 479 //Alpha Regs, but here now, for 480 //compiling sake 481 UNIQ, 482 LockAddr, 483 LockFlag 484 }; 485 486extern const Addr PageShift; 487extern const Addr PageBytes; 488extern const Addr PageMask; 489extern const Addr PageOffset; 490 491#if FULL_SYSTEM 492 493 typedef uint64_t InternalProcReg; 494 495#include "arch/mips/isa_fullsys_traits.hh" 496 497#else 498 enum { 499 NumInternalProcRegs = 0 500 }; 501#endif 502 503 typedef union { 504 IntReg intreg; 505 FloatReg fpreg; 506 MiscReg ctrlreg; 507 } AnyReg; 508 509 class RegFile { 510 protected: 511 IntRegFile intRegFile; // (signed) integer register file 512 FloatRegFile floatRegFile; // floating point register file 513 MiscRegFile miscRegFile; // control register file 514 515 public: 516 517 void clear() 518 { 519 bzero(&intRegFile, sizeof(intRegFile)); 520 bzero(&floatRegFile, sizeof(floatRegFile)); 521 bzero(&miscRegFile, sizeof(miscRegFile)); 522 } 523 524 MiscReg readMiscReg(int miscReg) 525 { 526 return miscRegFile.readReg(miscReg); 527 } 528 529 MiscReg readMiscRegWithEffect(int miscReg, 530 Fault &fault, ExecContext *xc) 531 { 532 fault = NoFault; 533 return miscRegFile.readRegWithEffect(miscReg, fault, xc); 534 } 535 536 Fault setMiscReg(int miscReg, const MiscReg &val) 537 { 538 return miscRegFile.setReg(miscReg, val); 539 } 540 541 Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, 542 ExecContext * xc) 543 { 544 return miscRegFile.setRegWithEffect(miscReg, val, xc); 545 } 546 547 FloatReg readFloatReg(int floatReg) 548 { 549 return floatRegFile.readReg(floatReg); 550 } 551 552 FloatReg readFloatReg(int floatReg, int width) 553 { 554 return readFloatReg(floatReg); 555 } 556 557 FloatRegBits readFloatRegBits(int floatReg) 558 { 559 return floatRegFile.readRegBits(floatReg); 560 } 561 562 FloatRegBits readFloatRegBits(int floatReg, int width) 563 { 564 return readFloatRegBits(floatReg); 565 } 566 567 Fault setFloatReg(int floatReg, const FloatReg &val) 568 { 569 return floatRegFile.setReg(floatReg, val); 570 } 571 572 Fault setFloatReg(int floatReg, const FloatReg &val, int width) 573 { 574 return setFloatReg(floatReg, val); 575 } 576 577 Fault setFloatRegBits(int floatReg, const FloatRegBits &val) 578 { 579 return floatRegFile.setRegBits(floatReg, val); 580 } 581 582 Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width) 583 { 584 return setFloatRegBits(floatReg, val); 585 } 586 587 IntReg readIntReg(int intReg) 588 { 589 return intRegFile.readReg(intReg); 590 } 591 592 Fault setIntReg(int intReg, const IntReg &val) 593 { 594 return intRegFile.setReg(intReg, val); 595 } 596 protected: 597 598 Addr pc; // program counter 599 Addr npc; // next-cycle program counter 600 Addr nnpc; // next-next-cycle program counter 601 // used to implement branch delay slot 602 // not real register 603 public: 604 Addr readPC() 605 { 606 return pc; 607 } 608 609 void setPC(Addr val) 610 { 611 pc = val; 612 } 613 614 Addr readNextPC() 615 { 616 return npc; 617 } 618 619 void setNextPC(Addr val) 620 { 621 npc = val; 622 } 623 624 Addr readNextNPC() 625 { 626 return nnpc; 627 } 628 629 void setNextNPC(Addr val) 630 { 631 nnpc = val; 632 } 633 634 MiscReg hi; // MIPS HI Register 635 MiscReg lo; // MIPS LO Register 636 637 638#if FULL_SYSTEM 639 IntReg palregs[NumIntRegs]; // PAL shadow registers 640 InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs 641 int intrflag; // interrupt flag 642 bool pal_shadow; // using pal_shadow registers 643 inline int instAsid() { return MIPS34K::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); } 644 inline int dataAsid() { return MIPS34K::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); } 645#endif // FULL_SYSTEM 646 647 //void initCP0Regs(); 648 void serialize(std::ostream &os); 649 void unserialize(Checkpoint *cp, const std::string §ion); 650 651 void createCP0Regs(); 652 void coldReset(); 653 654 typedef int ContextParam; 655 typedef int ContextVal; 656 657 void changeContext(ContextParam param, ContextVal val) 658 { 659 } 660 }; 661 662 StaticInstPtr decodeInst(ExtMachInst); 663 664 // return a no-op instruction... used for instruction fetch faults 665 extern const MachInst NoopMachInst; 666 667 enum annotes { 668 ANNOTE_NONE = 0, 669 // An impossible number for instruction annotations 670 ITOUCH_ANNOTE = 0xffffffff, 671 }; 672 673//void getMiscRegIdx(int reg_name,int &idx, int &sel); 674 675 static inline ExtMachInst 676 makeExtMI(MachInst inst, const uint64_t &pc) { 677#if FULL_SYSTEM 678 ExtMachInst ext_inst = inst; 679 if (pc && 0x1) 680 return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 681 else 682 return ext_inst; 683#else 684 return ExtMachInst(inst); 685#endif 686 } 687 688 static inline bool isCallerSaveIntegerRegister(unsigned int reg) { 689 panic("register classification not implemented"); 690 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 691 } 692 693 static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 694 panic("register classification not implemented"); 695 return (reg >= 9 && reg <= 15); 696 } 697 698 static inline bool isCallerSaveFloatRegister(unsigned int reg) { 699 panic("register classification not implemented"); 700 return false; 701 } 702 703 static inline bool isCalleeSaveFloatRegister(unsigned int reg) { 704 panic("register classification not implemented"); 705 return false; 706 } 707 708 static inline Addr alignAddress(const Addr &addr, 709 unsigned int nbytes) { 710 return (addr & ~(nbytes - 1)); 711 } 712 713 // Instruction address compression hooks 714 static inline Addr realPCToFetchPC(const Addr &addr) { 715 return addr; 716 } 717 718 static inline Addr fetchPCToRealPC(const Addr &addr) { 719 return addr; 720 } 721 722 // the size of "fetched" instructions (not necessarily the size 723 // of real instructions for PISA) 724 static inline size_t fetchInstSize() { 725 return sizeof(MachInst); 726 } 727 728 static inline MachInst makeRegisterCopy(int dest, int src) { 729 panic("makeRegisterCopy not implemented"); 730 return 0; 731 } 732 733 static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) 734 { 735 if (return_value.successful()) { 736 // no error 737 regs->setIntReg(SyscallSuccessReg, 0); 738 regs->setIntReg(ReturnValueReg1, return_value.value()); 739 } else { 740 // got an error, return details 741 regs->setIntReg(SyscallSuccessReg, (IntReg) -1); 742 regs->setIntReg(ReturnValueReg1, -return_value.value()); 743 } 744 } 745 746 // Machine operations 747 748 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 749 int regnum); 750 751 void restoreMachineReg(RegFile ®s, const AnyReg ®, 752 int regnum); 753 754#if 0 755 static void serializeSpecialRegs(const Serializable::Proxy &proxy, 756 const RegFile ®s); 757 758 static void unserializeSpecialRegs(const IniFile *db, 759 const std::string &category, 760 ConfigNode *node, 761 RegFile ®s); 762#endif 763 764 /** 765 * Function to insure ISA semantics about 0 registers. 766 * @param xc The execution context. 767 */ 768 template <class XC> 769 void zeroRegisters(XC *xc); 770 771 const Addr MaxAddr = (Addr)-1; 772}; 773 774#if FULL_SYSTEM 775//typedef TheISA::InternalProcReg InternalProcReg; 776//const int NumInternalProcRegs = TheISA::NumInternalProcRegs; 777//const int NumInterruptLevels = TheISA::NumInterruptLevels; 778 779#include "arch/mips/mips34k.hh" 780#endif 781 782using namespace MipsISA; 783 784#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 785