operands.isa revision 6338:14572c7334b5
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30// Jaidev Patwardhan 31 32def operand_types {{ 33 'sb' : ('signed int', 8), 34 'ub' : ('unsigned int', 8), 35 'sh' : ('signed int', 16), 36 'uh' : ('unsigned int', 16), 37 'sw' : ('signed int', 32), 38 'uw' : ('unsigned int', 32), 39 'sd' : ('signed int', 64), 40 'ud' : ('unsigned int', 64), 41 'sf' : ('float', 32), 42 'df' : ('float', 64), 43}}; 44 45def operands {{ 46 #General Purpose Integer Reg Operands 47 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), 48 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2), 49 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3), 50 51 #Immediate Value operand 52 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3), 53 54 #Operands used for Link or Syscall Insts 55 'R31': ('IntReg', 'uw','31','IsInteger', 4), 56 'R2': ('IntReg', 'uw','2', 'IsInteger', 5), 57 58 #Special Integer Reg operands 59 'LO0': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6), 60 'HI0': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7), 61 62 #Bitfield-dependent HI/LO Register Access 63 'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6), 64 'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7), 65 'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6), 66 'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7), 67 68 #DSP Special Purpose Integer Operands 69 'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8), 70 'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1), 71 'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1), 72 'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1), 73 'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1), 74 'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1), 75 'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1), 76 'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1), 77 'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1), 78 'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1), 79 'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1), 80 'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1), 81 'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1), 82 83 #Floating Point Reg Operands 84 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1), 85 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2), 86 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3), 87 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3), 88 89 #Special Purpose Floating Point Control Reg Operands 90 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1), 91 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2), 92 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3), 93 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3), 94 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3), 95 96 #Operands For Paired Singles FP Operations 97 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4), 98 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4), 99 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5), 100 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5), 101 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6), 102 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6), 103 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7), 104 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7), 105 106 #Status Control Reg 107 'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1), 108 109 #LL Flag 110 'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1), 111 112 # Index Register 113 'Index':('ControlReg','uw','MipsISA::Index',None,1), 114 115 116 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1), 117 118 #MT Control Regs 119 'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1), 120 'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1), 121 'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1), 122 'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1), 123 'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1), 124 'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1), 125 'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1), 126 'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1), 127 128 #CP0 Control Regs 129 'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1), 130 'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1), 131 'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1), 132 'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1), 133 'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1), 134 'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1), 135 'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1), 136 'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1), 137 'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1), 138 'Config': ('ControlReg','uw', 'MipsISA::Config',None,1), 139 'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1), 140 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1), 141 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1), 142 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1), 143 144 145 # named bitfields of Control Regs 146 'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 147 'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 148 'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 149 'Status_BEV': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 150 'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 151 'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 152 'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 153 'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), 154 'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 155 'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 156 'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), 157 'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3), 158 'Config_MT': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 1), 159 'Config1_CA': ('ControlBitfield', 'uw', 'MipsISA::Config1', None, 1), 160 'Config3_SP': ('ControlBitfield', 'uw', 'MipsISA::Config3', None, 1), 161 'PageGrain_ESP': ('ControlBitfield', 'uw', 'MipsISA::PageGrain', None, 1), 162 'Cause_EXCCODE': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4), 163 'Cause_TI': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4), 164 'IntCtl_IPTI': ('ControlBitfield', 'uw', 'MipsISA::IntCtl', None, 4), 165 'EntryHi_ASID': ('ControlBitfield', 'uw', 'MipsISA::EntryHi', None, 1), 166 'EntryLo0_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 167 'EntryLo0_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 3), 168 'EntryLo0_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 169 'EntryLo0_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 170 'EntryLo0_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), 171 'EntryLo1_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 172 'EntryLo1_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 3), 173 'EntryLo1_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 174 'EntryLo1_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 175 'EntryLo1_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), 176 177 # named bitfields of Debug Regs 178 'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), 179 'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), 180 181 #Memory Operand 182 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), 183 184 #Program Counter Operands 185 'NPC': ('NPC', 'uw', None, 'IsControl', 4), 186 'NNPC':('NNPC', 'uw', None, 'IsControl', 4) 187}}; 188