operands.isa revision 5222:bb733a878f85
1// -*- mode:c++ -*-
2
3// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
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5//  This software is part of the M5 simulator.
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34
35//Authors: Korey L. Sewell
36//         Jaidev Patwardhan
37
38def operand_types {{
39    'sb' : ('signed int', 8),
40    'ub' : ('unsigned int', 8),
41    'sh' : ('signed int', 16),
42    'uh' : ('unsigned int', 16),
43    'sw' : ('signed int', 32),
44    'uw' : ('unsigned int', 32),
45    'sd' : ('signed int', 64),
46    'ud' : ('unsigned int', 64),
47    'sf' : ('float', 32),
48    'df' : ('float', 64),
49}};
50
51def operands {{
52    #General Purpose Integer Reg Operands
53    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
54    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
55    'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
56
57    #Immediate Value operand
58    'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
59
60    #Operands used for Link or Syscall Insts
61    'R31': ('IntReg', 'uw','31','IsInteger', 4),
62    'R2':  ('IntReg', 'uw','2', 'IsInteger', 5),
63
64    #Special Integer Reg operands
65    'LO0':  ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6),
66    'HI0':  ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7),
67
68    #Bitfield-dependent HI/LO Register Access
69    'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6),
70    'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7),
71    'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6),
72    'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7),
73
74    #DSP Special Purpose Integer Operands
75    'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8),
76    'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1),
77    'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1),
78    'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1),
79    'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1),
80    'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1),
81    'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1),
82    'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1),
83    'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1),
84    'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1),
85    'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1),
86    'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1),
87    'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1),
88
89    #Floating Point Reg Operands
90    'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
91    'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
92    'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
93    'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
94
95    #Special Purpose Floating Point Control Reg Operands
96    'FIR':  ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
97    'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
98    'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
99    'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
100    'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
101
102    #Operands For Paired Singles FP Operations
103    'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
104    'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
105    'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
106    'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
107    'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
108    'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
109    'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
110    'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
111
112    #Status Control Reg
113    'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1),
114
115    #LL Flag
116    'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1),
117
118    # Index Register
119    'Index':('ControlReg','uw','MipsISA::Index',None,1),
120
121
122    #Special cases for when a Control Register Access is dependent on
123    #a combination of bitfield indices (handles MTCO & MFCO)
124    # Fixed to allow CP0 Register Offset
125    'CP0_RD_SEL': ('IControlReg', 'uw', '(RD << 3 | SEL) + Ctrl_Base_DepTag', None, 1),
126
127    #MT Control Regs
128    'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
129    'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1),
130    'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1),
131    'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1),
132    'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1),
133    'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1),
134    'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1),
135    'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1),
136
137    #CP0 Control Regs
138    'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1),
139    'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1),
140    'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1),
141    'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1),
142    'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1),
143    'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1),
144    'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1),
145    'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1),
146    'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1),
147    'Config': ('ControlReg','uw', 'MipsISA::Config',None,1),
148    'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1),
149    'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1),
150    'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1),
151    'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),
152
153
154    # named bitfields of Control Regs
155    'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
156    'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
157    'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
158    'Status_BEV': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
159    'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
160    'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
161    'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
162    'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
163    'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
164    'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
165    'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
166    'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3),
167    'Config_MT': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 1),
168    'Config1_CA': ('ControlBitfield', 'uw', 'MipsISA::Config1', None, 1),
169    'Config3_SP': ('ControlBitfield', 'uw', 'MipsISA::Config3', None, 1),
170    'PageGrain_ESP': ('ControlBitfield', 'uw', 'MipsISA::PageGrain', None, 1),
171    'Cause_EXCCODE': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4),
172    'Cause_TI': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4),
173    'IntCtl_IPTI': ('ControlBitfield', 'uw', 'MipsISA::IntCtl', None, 4),
174    'EntryHi_ASID': ('ControlBitfield', 'uw', 'MipsISA::EntryHi', None, 1),
175    'EntryLo0_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
176    'EntryLo0_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 3),
177    'EntryLo0_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
178    'EntryLo0_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
179    'EntryLo0_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
180    'EntryLo1_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
181    'EntryLo1_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 3),
182    'EntryLo1_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
183    'EntryLo1_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
184    'EntryLo1_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
185
186    # named bitfields of Debug Regs
187    'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),
188    'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),
189
190    #Memory Operand
191    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
192
193    #Program Counter Operands
194    'NPC': ('NPC', 'uw', None, 'IsControl', 4),
195    'NNPC':('NNPC', 'uw', None, 'IsControl', 4)
196}};
197