includes.isa revision 8564:f81bcb16fa1b
12381SN/A// -*- mode:c++ -*- 28922Swilliam.wang@arm.com 38922Swilliam.wang@arm.com// Copyright (c) 2007 MIPS Technologies, Inc. 48922Swilliam.wang@arm.com// All rights reserved. 58922Swilliam.wang@arm.com// 68922Swilliam.wang@arm.com// Redistribution and use in source and binary forms, with or without 78922Swilliam.wang@arm.com// modification, are permitted provided that the following conditions are 88922Swilliam.wang@arm.com// met: redistributions of source code must retain the above copyright 98922Swilliam.wang@arm.com// notice, this list of conditions and the following disclaimer; 108922Swilliam.wang@arm.com// redistributions in binary form must reproduce the above copyright 118922Swilliam.wang@arm.com// notice, this list of conditions and the following disclaimer in the 128922Swilliam.wang@arm.com// documentation and/or other materials provided with the distribution; 138922Swilliam.wang@arm.com// neither the name of the copyright holders nor the names of its 142381SN/A// contributors may be used to endorse or promote products derived from 152381SN/A// this software without specific prior written permission. 162381SN/A// 172381SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182381SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192381SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202381SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212381SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222381SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232381SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242381SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252381SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262381SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272381SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282381SN/A// 292381SN/A// Authors: Korey Sewell 302381SN/A 312381SN/A//////////////////////////////////////////////////////////////////// 322381SN/A// 332381SN/A// Output include file directives. 342381SN/A// 352381SN/A 362381SN/Aoutput header {{ 372381SN/A#include <iomanip> 382381SN/A#include <iostream> 392665Ssaidi@eecs.umich.edu#include <sstream> 402665Ssaidi@eecs.umich.edu 418922Swilliam.wang@arm.com#include "arch/mips/isa_traits.hh" 422381SN/A#include "arch/mips/types.hh" 432381SN/A#include "cpu/static_inst.hh" 442381SN/A#include "mem/packet.hh" 452381SN/A}}; 468922Swilliam.wang@arm.com 472381SN/Aoutput decoder {{ 482381SN/A#include <math.h> 492381SN/A 502381SN/A#include "arch/mips/dsp.hh" 512381SN/A#include "arch/mips/dt_constants.hh" 524762Snate@binkert.org#include "arch/mips/faults.hh" 539157Sandreas.hansson@arm.com#include "arch/mips/isa_traits.hh" 542381SN/A#include "arch/mips/mt_constants.hh" 552381SN/A#include "arch/mips/pra_constants.hh" 5613784Sgabeblack@google.com#include "arch/mips/utility.hh" 572381SN/A#include "base/loader/symtab.hh" 589157Sandreas.hansson@arm.com#include "base/cprintf.hh" 592381SN/A#include "cpu/thread_context.hh" 602381SN/A#include "mem/packet.hh" 6114261Sgabeblack@google.com#if defined(linux) 6214261Sgabeblack@google.com#include <fenv.h> 6314261Sgabeblack@google.com#endif 6414261Sgabeblack@google.com 652381SN/Ausing namespace MipsISA; 662381SN/A}}; 672381SN/A 68output exec {{ 69#include <math.h> 70 71#include "arch/generic/memhelpers.hh" 72#include "arch/mips/dsp.hh" 73#include "arch/mips/dt_constants.hh" 74#include "arch/mips/faults.hh" 75#include "arch/mips/isa_traits.hh" 76#include "arch/mips/mt.hh" 77#include "arch/mips/mt_constants.hh" 78#include "arch/mips/pagetable.hh" 79#include "arch/mips/pra_constants.hh" 80#include "arch/mips/tlb.hh" 81#include "arch/mips/utility.hh" 82#if defined(linux) 83#include <fenv.h> 84#endif 85 86#include "base/condcodes.hh" 87#include "cpu/base.hh" 88#include "cpu/exetrace.hh" 89#include "debug/MipsPRA.hh" 90#include "mem/packet.hh" 91#include "mem/packet_access.hh" 92#include "sim/eventq.hh" 93#include "sim/sim_events.hh" 94#include "sim/sim_exit.hh" 95 96using namespace MipsISA; 97}}; 98 99