util.isa revision 5268
19850Sandreas.hansson@arm.com// -*- mode:c++ -*- 29850Sandreas.hansson@arm.com 39850Sandreas.hansson@arm.com// Copyright (c) 2003-2005 The Regents of The University of Michigan 49850Sandreas.hansson@arm.com// Copyright (c) 2007 MIPS Technologies, Inc. 59850Sandreas.hansson@arm.com// All rights reserved. 69850Sandreas.hansson@arm.com// 79850Sandreas.hansson@arm.com// Redistribution and use in source and binary forms, with or without 89850Sandreas.hansson@arm.com// modification, are permitted provided that the following conditions are 99850Sandreas.hansson@arm.com// met: redistributions of source code must retain the above copyright 109850Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer; 119850Sandreas.hansson@arm.com// redistributions in binary form must reproduce the above copyright 129850Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer in the 139850Sandreas.hansson@arm.com// documentation and/or other materials provided with the distribution; 149850Sandreas.hansson@arm.com// neither the name of the copyright holders nor the names of its 159850Sandreas.hansson@arm.com// contributors may be used to endorse or promote products derived from 169850Sandreas.hansson@arm.com// this software without specific prior written permission. 179850Sandreas.hansson@arm.com// 189850Sandreas.hansson@arm.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 199850Sandreas.hansson@arm.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 209850Sandreas.hansson@arm.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 219850Sandreas.hansson@arm.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 229850Sandreas.hansson@arm.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 239850Sandreas.hansson@arm.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 249850Sandreas.hansson@arm.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 259850Sandreas.hansson@arm.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 269850Sandreas.hansson@arm.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 279850Sandreas.hansson@arm.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 289850Sandreas.hansson@arm.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 299850Sandreas.hansson@arm.com// 309850Sandreas.hansson@arm.com// Authors: Steve Reinhardt 319850Sandreas.hansson@arm.com// Korey Sewell 329850Sandreas.hansson@arm.com 339850Sandreas.hansson@arm.comlet {{ 349850Sandreas.hansson@arm.comdef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 359850Sandreas.hansson@arm.com postacc_code = '', base_class = 'Memory', 369850Sandreas.hansson@arm.com decode_template = BasicDecode, exec_template_base = ''): 379850Sandreas.hansson@arm.com # Make sure flags are in lists (convert to lists if not). 389850Sandreas.hansson@arm.com mem_flags = makeList(mem_flags) 399850Sandreas.hansson@arm.com inst_flags = makeList(inst_flags) 409850Sandreas.hansson@arm.com 419850Sandreas.hansson@arm.com # add hook to get effective addresses into execution trace output. 429850Sandreas.hansson@arm.com ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' 4312109SRekai.GonzalezAlberquilla@arm.com 4412104Snathanael.premillieu@arm.com # Some CPU models execute the memory operation as an atomic unit, 459850Sandreas.hansson@arm.com # while others want to separate them into an effective address 469850Sandreas.hansson@arm.com # computation and a memory access operation. As a result, we need 479850Sandreas.hansson@arm.com # to generate three StaticInst objects. Note that the latter two 489850Sandreas.hansson@arm.com # are nested inside the larger "atomic" one. 4913556Sgabeblack@google.com 5013556Sgabeblack@google.com # Generate InstObjParams for each of the three objects. Note that 5113556Sgabeblack@google.com # they differ only in the set of code objects contained (which in 529920Syasuko.eckert@amd.com # turn affects the object's overall operand list). 5313556Sgabeblack@google.com iop = InstObjParams(name, Name, base_class, 5412104Snathanael.premillieu@arm.com { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 559850Sandreas.hansson@arm.com inst_flags) 5612109SRekai.GonzalezAlberquilla@arm.com ea_iop = InstObjParams(name, Name, base_class, 5712109SRekai.GonzalezAlberquilla@arm.com { 'ea_code':ea_code }, 5812109SRekai.GonzalezAlberquilla@arm.com inst_flags) 5912109SRekai.GonzalezAlberquilla@arm.com memacc_iop = InstObjParams(name, Name, base_class, 6012109SRekai.GonzalezAlberquilla@arm.com { 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 6112109SRekai.GonzalezAlberquilla@arm.com inst_flags) 6212109SRekai.GonzalezAlberquilla@arm.com 6312109SRekai.GonzalezAlberquilla@arm.com if mem_flags: 6412109SRekai.GonzalezAlberquilla@arm.com s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 659850Sandreas.hansson@arm.com iop.constructor += s 669850Sandreas.hansson@arm.com memacc_iop.constructor += s 679850Sandreas.hansson@arm.com 68 # select templates 69 70 # The InitiateAcc template is the same for StoreCond templates as the 71 # corresponding Store template.. 72 StoreCondInitiateAcc = StoreInitiateAcc 73 74 memAccExecTemplate = eval(exec_template_base + 'MemAccExecute') 75 fullExecTemplate = eval(exec_template_base + 'Execute') 76 initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 77 completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 78 eaCompExecuteTemplate = eval('EACompExecute') 79 80 if (exec_template_base == 'Load' or exec_template_base == 'Store'): 81 memAccSizeTemplate = eval('LoadStoreMemAccSize') 82 else: 83 memAccSizeTemplate = eval('MiscMemAccSize') 84 85 # (header_output, decoder_output, decode_block, exec_output) 86 return (LoadStoreDeclare.subst(iop), 87 EACompConstructor.subst(ea_iop) 88 + MemAccConstructor.subst(memacc_iop) 89 + LoadStoreConstructor.subst(iop), 90 decode_template.subst(iop), 91 eaCompExecuteTemplate.subst(ea_iop) 92 + memAccExecTemplate.subst(memacc_iop) 93 + fullExecTemplate.subst(iop) 94 + initiateAccTemplate.subst(iop) 95 + completeAccTemplate.subst(iop) 96 + memAccSizeTemplate.subst(memacc_iop)) 97}}; 98 99output header {{ 100 std::string inst2string(MachInst machInst); 101}}; 102 103output decoder {{ 104 105std::string inst2string(MachInst machInst) 106{ 107 string str = ""; 108 uint32_t mask = 0x80000000; 109 110 for(int i=0; i < 32; i++) { 111 if ((machInst & mask) == 0) { 112 str += "0"; 113 } else { 114 str += "1"; 115 } 116 117 mask = mask >> 1; 118 } 119 120 return str; 121} 122 123}}; 124