mt.isa revision 5222:bb733a878f85 
1// -*- mode:c++ -*-
2
3// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
4
5//  This software is part of the M5 simulator.
6
7//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
8//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
9//  TO THESE TERMS AND CONDITIONS.
10
11//  Permission is granted to use, copy, create derivative works and
12//  distribute this software and such derivative works for any purpose,
13//  so long as (1) the copyright notice above, this grant of permission,
14//  and the disclaimer below appear in all copies and derivative works
15//  made, (2) the copyright notice above is augmented as appropriate to
16//  reflect the addition of any new copyrightable work in a derivative
17//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
18//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
19//  advertising or publicity pertaining to the use or distribution of
20//  this software without specific, written prior authorization.
21
22//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
23//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
24//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
26//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
27//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
28//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
29//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
30//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
31//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
32//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
33//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
34
35//Authors: Korey L. Sewell
36
37////////////////////////////////////////////////////////////////////
38//
39// MT instructions
40//
41
42output header {{
43        /**
44         * Base class for MIPS MT ASE operations.
45         */
46        class MTOp : public MipsStaticInst
47        {
48                protected:
49
50                /// Constructor
51                MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
52                    MipsStaticInst(mnem, _machInst, __opClass), user_mode(false)
53                {
54                }
55
56               std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
57
58                bool user_mode;
59        };
60
61        class MTUserModeOp : public MTOp
62        {
63                protected:
64
65                /// Constructor
66                MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
67                    MTOp(mnem, _machInst, __opClass)
68                {
69                    user_mode = true;
70                }
71
72            //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
73        };
74}};
75
76output decoder {{
77    std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
78    {
79        std::stringstream ss;
80
81        if (mnemonic == "mttc0" || mnemonic == "mftc0") {
82            ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
83        } else if (mnemonic == "mftgpr") {
84            ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
85        } else {
86            ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
87        }
88
89        return ss.str();
90    }
91}};
92
93output exec {{
94    void getThrRegExValues(%(CPU_exec_context)s *xc, unsigned &vpe_conf0, unsigned &tc_bind_mt, unsigned &tc_bind, unsigned &vpe_control, unsigned &mvp_conf0)
95    {
96        vpe_conf0 = xc->readMiscReg(VPEConf0);
97        tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag);
98        tc_bind = xc->readMiscReg(TCBind);
99        vpe_control = xc->readMiscReg(VPEControl);
100        mvp_conf0 = xc->readMiscReg(MVPConf0);
101    }
102
103    void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3)
104    {
105        config3 = xc->readMiscReg(Config3);
106    }
107}};
108
109def template ThreadRegisterExecute {{
110        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
111        {
112            Fault fault = NoFault;
113            int64_t data;
114            %(op_decl)s;
115            %(op_rd)s;
116
117            unsigned vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0;
118
119            getThrRegExValues(xc, vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0);
120
121            if (isCoprocessorEnabled(xc, 0)) {
122                if (bits(vpe_conf0, VPEC0_MVP) == 0 &&
123                    bits(tc_bind_mt, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) !=
124                    bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) {
125                    data = -1;
126                } else if (bits(vpe_control, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO) >
127                           bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO)) {
128                    data = -1;
129                } else {
130                    int top_bit = 0;
131                    int bottom_bit = 0;
132
133                    if (MT_H == 1) {
134                        top_bit = 63;
135                        bottom_bit = 32;
136                    } else {
137                        top_bit = 31;
138                        bottom_bit = 0;
139                    }
140
141                    %(code)s;
142                }
143            } else {
144                fault = new CoprocessorUnusableFault(0);
145            }
146
147            if(fault == NoFault)
148            {
149                %(op_wb)s;
150            }
151
152            return fault;
153        }
154}};
155
156def template MTExecute{{
157        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
158        {
159                Fault fault = NoFault;
160                %(op_decl)s;
161                %(op_rd)s;
162
163                unsigned config3;
164
165                getMTExValues(xc, config3);
166
167                if (isCoprocessorEnabled(xc, 0)) {
168                    if (bits(config3, CFG3_MT) == 1) {
169                        %(code)s;
170                    } else {
171                        fault = new ReservedInstructionFault();
172                    }
173                } else {
174                    fault = new CoprocessorUnusableFault(0);
175                }
176
177                if(fault == NoFault)
178                {
179                    %(op_wb)s;
180                }
181                return fault;
182        }
183}};
184
185// Primary format for integer operate instructions:
186def format MT_Control(code, *opt_flags) {{
187        inst_flags = ('IsNonSpeculative', )
188        op_type = 'MTOp'
189
190        for x in opt_flags:
191            if x == 'UserMode':
192                op_type = 'MTUserModeOp'
193            else:
194                inst_flags += (x, )
195
196        iop = InstObjParams(name, Name, op_type, code, inst_flags)
197        header_output = BasicDeclare.subst(iop)
198        decoder_output = BasicConstructor.subst(iop)
199        decode_block = BasicDecode.subst(iop)
200        exec_output = MTExecute.subst(iop)
201}};
202
203def format MT_MFTR(code, *flags) {{
204        flags += ('IsNonSpeculative', )
205#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
206
207        code += 'if (MT_H == 1) {\n'
208        code += 'data = bits(data, top_bit, bottom_bit);\n'
209        code += '}\n'
210        code += 'Rd = data;\n'
211
212        iop = InstObjParams(name, Name, 'MTOp', code, flags)
213        header_output = BasicDeclare.subst(iop)
214        decoder_output = BasicConstructor.subst(iop)
215        decode_block = BasicDecode.subst(iop)
216        exec_output = ThreadRegisterExecute.subst(iop)
217}};
218
219def format MT_MTTR(code, *flags) {{
220        flags += ('IsNonSpeculative', )
221#        code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
222        iop = InstObjParams(name, Name, 'MTOp', code, flags)
223        header_output = BasicDeclare.subst(iop)
224        decoder_output = BasicConstructor.subst(iop)
225        decode_block = BasicDecode.subst(iop)
226        exec_output = ThreadRegisterExecute.subst(iop)
227}};
228