mt.isa revision 6376
12686Sksewell@umich.edu// -*- mode:c++ -*- 22686Sksewell@umich.edu 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Korey Sewell 302706Sksewell@umich.edu 312686Sksewell@umich.edu//////////////////////////////////////////////////////////////////// 322686Sksewell@umich.edu// 332686Sksewell@umich.edu// MT instructions 342686Sksewell@umich.edu// 352686Sksewell@umich.edu 362686Sksewell@umich.eduoutput header {{ 372686Sksewell@umich.edu /** 382741Sksewell@umich.edu * Base class for MIPS MT ASE operations. 392686Sksewell@umich.edu */ 404661Sksewell@umich.edu class MTOp : public MipsStaticInst 412686Sksewell@umich.edu { 422686Sksewell@umich.edu protected: 432686Sksewell@umich.edu 442686Sksewell@umich.edu /// Constructor 454661Sksewell@umich.edu MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 464661Sksewell@umich.edu MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 472686Sksewell@umich.edu { 482686Sksewell@umich.edu } 492686Sksewell@umich.edu 504661Sksewell@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 514661Sksewell@umich.edu 524661Sksewell@umich.edu bool user_mode; 534661Sksewell@umich.edu }; 544661Sksewell@umich.edu 554661Sksewell@umich.edu class MTUserModeOp : public MTOp 564661Sksewell@umich.edu { 574661Sksewell@umich.edu protected: 584661Sksewell@umich.edu 594661Sksewell@umich.edu /// Constructor 604661Sksewell@umich.edu MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 614661Sksewell@umich.edu MTOp(mnem, _machInst, __opClass) 624661Sksewell@umich.edu { 634661Sksewell@umich.edu user_mode = true; 644661Sksewell@umich.edu } 654661Sksewell@umich.edu 664661Sksewell@umich.edu //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 672686Sksewell@umich.edu }; 682686Sksewell@umich.edu}}; 692686Sksewell@umich.edu 702686Sksewell@umich.eduoutput decoder {{ 714661Sksewell@umich.edu std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 724661Sksewell@umich.edu { 734661Sksewell@umich.edu std::stringstream ss; 744661Sksewell@umich.edu 755269Sksewell@umich.edu if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) { 764661Sksewell@umich.edu ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 775269Sksewell@umich.edu } else if (strcmp(mnemonic,"mftgpr") == 0) { 784661Sksewell@umich.edu ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 794661Sksewell@umich.edu } else { 804661Sksewell@umich.edu ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 814661Sksewell@umich.edu } 824661Sksewell@umich.edu 834661Sksewell@umich.edu return ss.str(); 844661Sksewell@umich.edu } 854661Sksewell@umich.edu}}; 864661Sksewell@umich.edu 874661Sksewell@umich.eduoutput exec {{ 886376Sgblack@eecs.umich.edu void getThrRegExValues(%(CPU_exec_context)s *xc, 896376Sgblack@eecs.umich.edu VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt, 906376Sgblack@eecs.umich.edu TCBindReg &tc_bind, VPEControlReg &vpe_control, 916376Sgblack@eecs.umich.edu MVPConf0Reg &mvp_conf0) 924661Sksewell@umich.edu { 934661Sksewell@umich.edu vpe_conf0 = xc->readMiscReg(VPEConf0); 944661Sksewell@umich.edu tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag); 954661Sksewell@umich.edu tc_bind = xc->readMiscReg(TCBind); 964661Sksewell@umich.edu vpe_control = xc->readMiscReg(VPEControl); 974661Sksewell@umich.edu mvp_conf0 = xc->readMiscReg(MVPConf0); 984661Sksewell@umich.edu } 994661Sksewell@umich.edu 1006376Sgblack@eecs.umich.edu void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3) 1014661Sksewell@umich.edu { 1025222Sksewell@umich.edu config3 = xc->readMiscReg(Config3); 1034661Sksewell@umich.edu } 1044661Sksewell@umich.edu}}; 1054661Sksewell@umich.edu 1064661Sksewell@umich.edudef template ThreadRegisterExecute {{ 1074661Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1082686Sksewell@umich.edu { 1094661Sksewell@umich.edu Fault fault = NoFault; 1104661Sksewell@umich.edu int64_t data; 1114661Sksewell@umich.edu %(op_decl)s; 1124661Sksewell@umich.edu %(op_rd)s; 1134661Sksewell@umich.edu 1146376Sgblack@eecs.umich.edu VPEConf0Reg vpeConf0; 1156376Sgblack@eecs.umich.edu TCBindReg tcBindMT; 1166376Sgblack@eecs.umich.edu TCBindReg tcBind; 1176376Sgblack@eecs.umich.edu VPEControlReg vpeControl; 1186376Sgblack@eecs.umich.edu MVPConf0Reg mvpConf0; 1194661Sksewell@umich.edu 1206376Sgblack@eecs.umich.edu getThrRegExValues(xc, vpeConf0, tcBindMT, 1216376Sgblack@eecs.umich.edu tcBind, vpeControl, mvpConf0); 1224661Sksewell@umich.edu 1234661Sksewell@umich.edu if (isCoprocessorEnabled(xc, 0)) { 1246376Sgblack@eecs.umich.edu if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) { 1254661Sksewell@umich.edu data = -1; 1266376Sgblack@eecs.umich.edu } else if (vpeControl.targTC > mvpConf0.ptc) { 1274661Sksewell@umich.edu data = -1; 1284661Sksewell@umich.edu } else { 1294661Sksewell@umich.edu int top_bit = 0; 1304661Sksewell@umich.edu int bottom_bit = 0; 1314661Sksewell@umich.edu 1324661Sksewell@umich.edu if (MT_H == 1) { 1334661Sksewell@umich.edu top_bit = 63; 1344661Sksewell@umich.edu bottom_bit = 32; 1354661Sksewell@umich.edu } else { 1364661Sksewell@umich.edu top_bit = 31; 1374661Sksewell@umich.edu bottom_bit = 0; 1384661Sksewell@umich.edu } 1394661Sksewell@umich.edu 1404661Sksewell@umich.edu %(code)s; 1414661Sksewell@umich.edu } 1424661Sksewell@umich.edu } else { 1435222Sksewell@umich.edu fault = new CoprocessorUnusableFault(0); 1444661Sksewell@umich.edu } 1454661Sksewell@umich.edu 1464661Sksewell@umich.edu if(fault == NoFault) 1474661Sksewell@umich.edu { 1484661Sksewell@umich.edu %(op_wb)s; 1494661Sksewell@umich.edu } 1504661Sksewell@umich.edu 1514661Sksewell@umich.edu return fault; 1522686Sksewell@umich.edu } 1532686Sksewell@umich.edu}}; 1542686Sksewell@umich.edu 1554661Sksewell@umich.edudef template MTExecute{{ 1562686Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1572686Sksewell@umich.edu { 1584661Sksewell@umich.edu Fault fault = NoFault; 1594661Sksewell@umich.edu %(op_decl)s; 1604661Sksewell@umich.edu %(op_rd)s; 1612686Sksewell@umich.edu 1626376Sgblack@eecs.umich.edu Config3Reg config3; 1634661Sksewell@umich.edu 1644661Sksewell@umich.edu getMTExValues(xc, config3); 1654661Sksewell@umich.edu 1664661Sksewell@umich.edu if (isCoprocessorEnabled(xc, 0)) { 1676376Sgblack@eecs.umich.edu if (config3.mt == 1) { 1684661Sksewell@umich.edu %(code)s; 1694661Sksewell@umich.edu } else { 1704661Sksewell@umich.edu fault = new ReservedInstructionFault(); 1714661Sksewell@umich.edu } 1724661Sksewell@umich.edu } else { 1735222Sksewell@umich.edu fault = new CoprocessorUnusableFault(0); 1744661Sksewell@umich.edu } 1754661Sksewell@umich.edu 1764661Sksewell@umich.edu if(fault == NoFault) 1774661Sksewell@umich.edu { 1784661Sksewell@umich.edu %(op_wb)s; 1794661Sksewell@umich.edu } 1804661Sksewell@umich.edu return fault; 1812686Sksewell@umich.edu } 1822686Sksewell@umich.edu}}; 1832686Sksewell@umich.edu 1842686Sksewell@umich.edu// Primary format for integer operate instructions: 1854661Sksewell@umich.edudef format MT_Control(code, *opt_flags) {{ 1864661Sksewell@umich.edu inst_flags = ('IsNonSpeculative', ) 1874661Sksewell@umich.edu op_type = 'MTOp' 1884661Sksewell@umich.edu 1894661Sksewell@umich.edu for x in opt_flags: 1904661Sksewell@umich.edu if x == 'UserMode': 1914661Sksewell@umich.edu op_type = 'MTUserModeOp' 1924661Sksewell@umich.edu else: 1934661Sksewell@umich.edu inst_flags += (x, ) 1944661Sksewell@umich.edu 1954661Sksewell@umich.edu iop = InstObjParams(name, Name, op_type, code, inst_flags) 1962686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 1972686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 1982686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 1994661Sksewell@umich.edu exec_output = MTExecute.subst(iop) 2002686Sksewell@umich.edu}}; 2014661Sksewell@umich.edu 2024661Sksewell@umich.edudef format MT_MFTR(code, *flags) {{ 2034661Sksewell@umich.edu flags += ('IsNonSpeculative', ) 2045715Shsul@eecs.umich.edu# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2054661Sksewell@umich.edu 2064661Sksewell@umich.edu code += 'if (MT_H == 1) {\n' 2074661Sksewell@umich.edu code += 'data = bits(data, top_bit, bottom_bit);\n' 2084661Sksewell@umich.edu code += '}\n' 2094661Sksewell@umich.edu code += 'Rd = data;\n' 2104661Sksewell@umich.edu 2114661Sksewell@umich.edu iop = InstObjParams(name, Name, 'MTOp', code, flags) 2124661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2134661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2144661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2154661Sksewell@umich.edu exec_output = ThreadRegisterExecute.subst(iop) 2164661Sksewell@umich.edu}}; 2174661Sksewell@umich.edu 2184661Sksewell@umich.edudef format MT_MTTR(code, *flags) {{ 2194661Sksewell@umich.edu flags += ('IsNonSpeculative', ) 2205715Shsul@eecs.umich.edu# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2214661Sksewell@umich.edu iop = InstObjParams(name, Name, 'MTOp', code, flags) 2224661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2234661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2244661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2254661Sksewell@umich.edu exec_output = ThreadRegisterExecute.subst(iop) 2264661Sksewell@umich.edu}}; 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