mt.isa revision 5268
12124SN/A// -*- mode:c++ -*- 22124SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Korey Sewell 305268Sksewell@umich.edu 312022SN/A//////////////////////////////////////////////////////////////////// 322649Ssaidi@eecs.umich.edu// 332649Ssaidi@eecs.umich.edu// MT instructions 342706Sksewell@umich.edu// 352649Ssaidi@eecs.umich.edu 362649Ssaidi@eecs.umich.eduoutput header {{ 372022SN/A /** 382124SN/A * Base class for MIPS MT ASE operations. 392124SN/A */ 402124SN/A class MTOp : public MipsStaticInst 412124SN/A { 422124SN/A protected: 432124SN/A 442124SN/A /// Constructor 455736Snate@binkert.org MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 462239SN/A MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 472124SN/A { 482124SN/A } 492124SN/A 502124SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 516207Sksewell@umich.edu 522124SN/A bool user_mode; 532742Sksewell@umich.edu }; 542022SN/A 552124SN/A class MTUserModeOp : public MTOp 562022SN/A { 572124SN/A protected: 582124SN/A 592124SN/A /// Constructor 602124SN/A MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 612742Sksewell@umich.edu MTOp(mnem, _machInst, __opClass) 622742Sksewell@umich.edu { 632742Sksewell@umich.edu user_mode = true; 642742Sksewell@umich.edu } 652742Sksewell@umich.edu 662742Sksewell@umich.edu //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 672742Sksewell@umich.edu }; 682742Sksewell@umich.edu}}; 696207Sksewell@umich.edu 706207Sksewell@umich.eduoutput decoder {{ 712742Sksewell@umich.edu std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 722742Sksewell@umich.edu { 732742Sksewell@umich.edu std::stringstream ss; 742742Sksewell@umich.edu 752742Sksewell@umich.edu if (mnemonic == "mttc0" || mnemonic == "mftc0") { 762742Sksewell@umich.edu ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 772022SN/A } else if (mnemonic == "mftgpr") { 782022SN/A ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 792124SN/A } else { 802022SN/A ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 812124SN/A } 822124SN/A 832124SN/A return ss.str(); 842742Sksewell@umich.edu } 852239SN/A}}; 862124SN/A 872124SN/Aoutput exec {{ 882742Sksewell@umich.edu void getThrRegExValues(%(CPU_exec_context)s *xc, unsigned &vpe_conf0, unsigned &tc_bind_mt, unsigned &tc_bind, unsigned &vpe_control, unsigned &mvp_conf0) 892742Sksewell@umich.edu { 902742Sksewell@umich.edu vpe_conf0 = xc->readMiscReg(VPEConf0); 912742Sksewell@umich.edu tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag); 922742Sksewell@umich.edu tc_bind = xc->readMiscReg(TCBind); 932742Sksewell@umich.edu vpe_control = xc->readMiscReg(VPEControl); 942742Sksewell@umich.edu mvp_conf0 = xc->readMiscReg(MVPConf0); 952742Sksewell@umich.edu } 964661Sksewell@umich.edu 974661Sksewell@umich.edu void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3) 984661Sksewell@umich.edu { 999554Sandreas.hansson@arm.com config3 = xc->readMiscReg(Config3); 10012234Sgabeblack@google.com } 1019554Sandreas.hansson@arm.com}}; 1029554Sandreas.hansson@arm.com 1039554Sandreas.hansson@arm.comdef template ThreadRegisterExecute {{ 1044661Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1054661Sksewell@umich.edu { 1064661Sksewell@umich.edu Fault fault = NoFault; 1074661Sksewell@umich.edu int64_t data; 10812234Sgabeblack@google.com %(op_decl)s; 1094661Sksewell@umich.edu %(op_rd)s; 1104661Sksewell@umich.edu 1115222Sksewell@umich.edu unsigned vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0; 1124661Sksewell@umich.edu 1134661Sksewell@umich.edu getThrRegExValues(xc, vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0); 1145222Sksewell@umich.edu 1154661Sksewell@umich.edu if (isCoprocessorEnabled(xc, 0)) { 1164661Sksewell@umich.edu if (bits(vpe_conf0, VPEC0_MVP) == 0 && 1175222Sksewell@umich.edu bits(tc_bind_mt, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) != 1184661Sksewell@umich.edu bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) { 1194661Sksewell@umich.edu data = -1; 1205222Sksewell@umich.edu } else if (bits(vpe_control, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO) > 1214661Sksewell@umich.edu bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO)) { 1224661Sksewell@umich.edu data = -1; 1234661Sksewell@umich.edu } else { 1244661Sksewell@umich.edu int top_bit = 0; 1254661Sksewell@umich.edu int bottom_bit = 0; 1264661Sksewell@umich.edu 1274661Sksewell@umich.edu if (MT_H == 1) { 1284661Sksewell@umich.edu top_bit = 63; 1294661Sksewell@umich.edu bottom_bit = 32; 1304661Sksewell@umich.edu } else { 1314661Sksewell@umich.edu top_bit = 31; 1322022SN/A bottom_bit = 0; 1332022SN/A } 1342124SN/A 1352124SN/A %(code)s; 1362124SN/A } 1372124SN/A } else { 1382124SN/A fault = new CoprocessorUnusableFault(0); 1392124SN/A } 1402124SN/A 1412124SN/A if(fault == NoFault) 1422124SN/A { 1434661Sksewell@umich.edu %(op_wb)s; 1442124SN/A } 1452124SN/A 1462124SN/A return fault; 1476207Sksewell@umich.edu } 1486207Sksewell@umich.edu}}; 1492124SN/A 1502124SN/Adef template MTExecute{{ 1512124SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1522124SN/A { 1532022SN/A Fault fault = NoFault; 1542022SN/A %(op_decl)s; 1556207Sksewell@umich.edu %(op_rd)s; 15612234Sgabeblack@google.com 1576207Sksewell@umich.edu unsigned config3; 1582124SN/A 1592124SN/A getMTExValues(xc, config3); 16012234Sgabeblack@google.com 1612022SN/A if (isCoprocessorEnabled(xc, 0)) { 1622124SN/A if (bits(config3, CFG3_MT) == 1) { 1632124SN/A %(code)s; 1642124SN/A } else { 16512234Sgabeblack@google.com fault = new ReservedInstructionFault(); 1662124SN/A } 1672124SN/A } else { 1686207Sksewell@umich.edu fault = new CoprocessorUnusableFault(0); 16910184SCurtis.Dunham@arm.com } 1706207Sksewell@umich.edu 1712124SN/A if(fault == NoFault) 1723953Sstever@eecs.umich.edu { 1732124SN/A %(op_wb)s; 1743953Sstever@eecs.umich.edu } 1752124SN/A return fault; 1763953Sstever@eecs.umich.edu } 1772124SN/A}}; 1782132SN/A 17912234Sgabeblack@google.com// Primary format for integer operate instructions: 1802124SN/Adef format MT_Control(code, *opt_flags) {{ 1812124SN/A inst_flags = ('IsNonSpeculative', ) 1822132SN/A op_type = 'MTOp' 1832124SN/A 1845222Sksewell@umich.edu for x in opt_flags: 1855222Sksewell@umich.edu if x == 'UserMode': 1865222Sksewell@umich.edu op_type = 'MTUserModeOp' 1875222Sksewell@umich.edu else: 1885222Sksewell@umich.edu inst_flags += (x, ) 1895222Sksewell@umich.edu 1905222Sksewell@umich.edu iop = InstObjParams(name, Name, op_type, code, inst_flags) 1912124SN/A header_output = BasicDeclare.subst(iop) 1922124SN/A decoder_output = BasicConstructor.subst(iop) 1933953Sstever@eecs.umich.edu decode_block = BasicDecode.subst(iop) 1942124SN/A exec_output = MTExecute.subst(iop) 1954661Sksewell@umich.edu}}; 1962124SN/A 1972124SN/Adef format MT_MFTR(code, *flags) {{ 1982124SN/A flags += ('IsNonSpeculative', ) 1992124SN/A# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2002124SN/A 2012124SN/A code += 'if (MT_H == 1) {\n' 2022124SN/A code += 'data = bits(data, top_bit, bottom_bit);\n' 2032124SN/A code += '}\n' 2042124SN/A code += 'Rd = data;\n' 20512234Sgabeblack@google.com 2062124SN/A iop = InstObjParams(name, Name, 'MTOp', code, flags) 2072124SN/A header_output = BasicDeclare.subst(iop) 2082124SN/A decoder_output = BasicConstructor.subst(iop) 2092132SN/A decode_block = BasicDecode.subst(iop) 2102124SN/A exec_output = ThreadRegisterExecute.subst(iop) 2115222Sksewell@umich.edu}}; 2125222Sksewell@umich.edu 2135222Sksewell@umich.edudef format MT_MTTR(code, *flags) {{ 2145222Sksewell@umich.edu flags += ('IsNonSpeculative', ) 2155222Sksewell@umich.edu# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2165222Sksewell@umich.edu iop = InstObjParams(name, Name, 'MTOp', code, flags) 2175222Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2182124SN/A decoder_output = BasicConstructor.subst(iop) 2192124SN/A decode_block = BasicDecode.subst(iop) 2202124SN/A exec_output = ThreadRegisterExecute.subst(iop) 2212124SN/A}}; 2222124SN/A