mt.isa revision 4661
12391SN/A// -*- mode:c++ -*- 28931Sandreas.hansson@arm.com 38931Sandreas.hansson@arm.com// Copyright (c) 2006 The Regents of The University of Michigan 48931Sandreas.hansson@arm.com// All rights reserved. 58931Sandreas.hansson@arm.com// 68931Sandreas.hansson@arm.com// Redistribution and use in source and binary forms, with or without 78931Sandreas.hansson@arm.com// modification, are permitted provided that the following conditions are 88931Sandreas.hansson@arm.com// met: redistributions of source code must retain the above copyright 98931Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer; 108931Sandreas.hansson@arm.com// redistributions in binary form must reproduce the above copyright 118931Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer in the 128931Sandreas.hansson@arm.com// documentation and/or other materials provided with the distribution; 138931Sandreas.hansson@arm.com// neither the name of the copyright holders nor the names of its 142391SN/A// contributors may be used to endorse or promote products derived from 152391SN/A// this software without specific prior written permission. 162391SN/A// 172391SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182391SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192391SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202391SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212391SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222391SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232391SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242391SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252391SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262391SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272391SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282391SN/A// 292391SN/A// Authors: Korey Sewell 302391SN/A 312391SN/A//////////////////////////////////////////////////////////////////// 322391SN/A// 332391SN/A// MT instructions 342391SN/A// 352391SN/A 362391SN/Aoutput header {{ 372391SN/A /** 382391SN/A * Base class for MIPS MT ASE operations. 392665SN/A */ 402665SN/A class MTOp : public MipsStaticInst 418931Sandreas.hansson@arm.com { 422391SN/A protected: 432391SN/A 448931Sandreas.hansson@arm.com /// Constructor 458931Sandreas.hansson@arm.com MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 468931Sandreas.hansson@arm.com MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 472391SN/A { 482391SN/A } 4912492Sodanrc@yahoo.com.br 5012492Sodanrc@yahoo.com.br std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 512391SN/A 522462SN/A bool user_mode; 538931Sandreas.hansson@arm.com }; 548719SN/A 552462SN/A class MTUserModeOp : public MTOp 569053Sdam.sunwoo@arm.com { 579053Sdam.sunwoo@arm.com protected: 589053Sdam.sunwoo@arm.com 598931Sandreas.hansson@arm.com /// Constructor 609293Sandreas.hansson@arm.com MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 619293Sandreas.hansson@arm.com MTOp(mnem, _machInst, __opClass) 629293Sandreas.hansson@arm.com { 639293Sandreas.hansson@arm.com user_mode = true; 649293Sandreas.hansson@arm.com } 659293Sandreas.hansson@arm.com 669293Sandreas.hansson@arm.com //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 679293Sandreas.hansson@arm.com }; 689293Sandreas.hansson@arm.com}}; 699293Sandreas.hansson@arm.com 709293Sandreas.hansson@arm.comoutput decoder {{ 719293Sandreas.hansson@arm.com std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 729293Sandreas.hansson@arm.com { 739293Sandreas.hansson@arm.com std::stringstream ss; 749293Sandreas.hansson@arm.com 759293Sandreas.hansson@arm.com if (mnemonic == "mttc0" || mnemonic == "mftc0") { 769293Sandreas.hansson@arm.com ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 7711005Sandreas.sandberg@arm.com } else if (mnemonic == "mftgpr") { 789293Sandreas.hansson@arm.com ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 799293Sandreas.hansson@arm.com } else { 809293Sandreas.hansson@arm.com ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 819293Sandreas.hansson@arm.com } 829293Sandreas.hansson@arm.com 839293Sandreas.hansson@arm.com return ss.str(); 849293Sandreas.hansson@arm.com } 859293Sandreas.hansson@arm.com}}; 869293Sandreas.hansson@arm.com 879293Sandreas.hansson@arm.comoutput exec {{ 889293Sandreas.hansson@arm.com void getThrRegExValues(%(CPU_exec_context)s *xc, unsigned &vpe_conf0, unsigned &tc_bind_mt, unsigned &tc_bind, unsigned &vpe_control, unsigned &mvp_conf0) 899293Sandreas.hansson@arm.com { 909293Sandreas.hansson@arm.com vpe_conf0 = xc->readMiscReg(VPEConf0); 919293Sandreas.hansson@arm.com tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag); 929293Sandreas.hansson@arm.com tc_bind = xc->readMiscReg(TCBind); 939293Sandreas.hansson@arm.com vpe_control = xc->readMiscReg(VPEControl); 949293Sandreas.hansson@arm.com mvp_conf0 = xc->readMiscReg(MVPConf0); 959293Sandreas.hansson@arm.com } 969293Sandreas.hansson@arm.com 978931Sandreas.hansson@arm.com void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3) 988931Sandreas.hansson@arm.com { 998931Sandreas.hansson@arm.com config3 = xc->readMiscReg(Config3_MT); 1008931Sandreas.hansson@arm.com } 1018931Sandreas.hansson@arm.com}}; 1028931Sandreas.hansson@arm.com 1038931Sandreas.hansson@arm.comdef template ThreadRegisterExecute {{ 1042391SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1056107SN/A { 1066107SN/A Fault fault = NoFault; 1078931Sandreas.hansson@arm.com int64_t data; 1089235Sandreas.hansson@arm.com %(op_decl)s; 1092413SN/A %(op_rd)s; 1108931Sandreas.hansson@arm.com 1118931Sandreas.hansson@arm.com unsigned vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0; 1122413SN/A 1138931Sandreas.hansson@arm.com getThrRegExValues(xc, vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0); 11411614Sdavid.j.hashe@gmail.com 1152413SN/A if (isCoprocessorEnabled(xc, 0)) { 1168931Sandreas.hansson@arm.com if (bits(vpe_conf0, VPEC0_MVP) == 0 && 11711614Sdavid.j.hashe@gmail.com bits(tc_bind_mt, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) != 11811614Sdavid.j.hashe@gmail.com bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) { 11911614Sdavid.j.hashe@gmail.com data = -1; 12011614Sdavid.j.hashe@gmail.com } else if (bits(vpe_control, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO) > 1213170SN/A bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO)) { 1223170SN/A data = -1; 1233170SN/A } else { 1243170SN/A int top_bit = 0; 1253170SN/A int bottom_bit = 0; 1263170SN/A 1273170SN/A if (MT_H == 1) { 1284626SN/A top_bit = 63; 1293170SN/A bottom_bit = 32; 1303170SN/A } else { 1313170SN/A top_bit = 31; 1323170SN/A bottom_bit = 0; 1334626SN/A } 1343170SN/A 1353170SN/A %(code)s; 1363170SN/A } 1373170SN/A } else { 1383170SN/A fault = new CoprocessorUnusableFault(); 1393170SN/A } 1403170SN/A 1413170SN/A if(fault == NoFault) 1424626SN/A { 1434626SN/A %(op_wb)s; 1443170SN/A } 1453170SN/A 1466102SN/A return fault; 1476102SN/A } 1484040SN/A}}; 1493170SN/A 1506102SN/Adef template MTExecute{{ 1513170SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1523170SN/A { 1534626SN/A Fault fault = NoFault; 1543170SN/A %(op_decl)s; 1553170SN/A %(op_rd)s; 1563170SN/A 1578719SN/A unsigned config3; 1589053Sdam.sunwoo@arm.com 1598719SN/A getMTExValues(xc, config3); 1609053Sdam.sunwoo@arm.com 1618719SN/A if (isCoprocessorEnabled(xc, 0)) { 1629053Sdam.sunwoo@arm.com if (bits(config3, CFG3_MT) == 1) { 1638719SN/A %(code)s; 1649053Sdam.sunwoo@arm.com } else { 1658719SN/A fault = new ReservedInstructionFault(); 1669053Sdam.sunwoo@arm.com } 1678719SN/A } else { 1689053Sdam.sunwoo@arm.com fault = new CoprocessorUnusableFault(); 1698719SN/A } 1708719SN/A 1718719SN/A if(fault == NoFault) 1728719SN/A { 1738719SN/A %(op_wb)s; 1748719SN/A } 1758719SN/A return fault; 1768719SN/A } 1778719SN/A}}; 1789053Sdam.sunwoo@arm.com 1799053Sdam.sunwoo@arm.com// Primary format for integer operate instructions: 1809053Sdam.sunwoo@arm.comdef format MT_Control(code, *opt_flags) {{ 1819053Sdam.sunwoo@arm.com inst_flags = ('IsNonSpeculative', ) 1829053Sdam.sunwoo@arm.com op_type = 'MTOp' 1839053Sdam.sunwoo@arm.com 1849053Sdam.sunwoo@arm.com for x in opt_flags: 1858931Sandreas.hansson@arm.com if x == 'UserMode': 1868931Sandreas.hansson@arm.com op_type = 'MTUserModeOp' 1878931Sandreas.hansson@arm.com else: 1888931Sandreas.hansson@arm.com inst_flags += (x, ) 1898931Sandreas.hansson@arm.com 1908931Sandreas.hansson@arm.com iop = InstObjParams(name, Name, op_type, code, inst_flags) 1918931Sandreas.hansson@arm.com header_output = BasicDeclare.subst(iop) 1922391SN/A decoder_output = BasicConstructor.subst(iop) 1932391SN/A decode_block = BasicDecode.subst(iop) 1948931Sandreas.hansson@arm.com exec_output = MTExecute.subst(iop) 1958931Sandreas.hansson@arm.com}}; 1968931Sandreas.hansson@arm.com 1978931Sandreas.hansson@arm.comdef format MT_MFTR(code, *flags) {{ 1989293Sandreas.hansson@arm.com flags += ('IsNonSpeculative', ) 1999293Sandreas.hansson@arm.com# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2009293Sandreas.hansson@arm.com 20110466Sandreas.hansson@arm.com code += 'if (MT_H == 1) {\n' 20210466Sandreas.hansson@arm.com code += 'data = bits(data, top_bit, bottom_bit);\n' 20311169Sandreas.hansson@arm.com code += '}\n' 20410466Sandreas.hansson@arm.com code += 'Rd = data;\n' 20510466Sandreas.hansson@arm.com 2069293Sandreas.hansson@arm.com iop = InstObjParams(name, Name, 'MTOp', code, flags) 2079293Sandreas.hansson@arm.com header_output = BasicDeclare.subst(iop) 2089293Sandreas.hansson@arm.com decoder_output = BasicConstructor.subst(iop) 2099293Sandreas.hansson@arm.com decode_block = BasicDecode.subst(iop) 2109293Sandreas.hansson@arm.com exec_output = ThreadRegisterExecute.subst(iop) 2119293Sandreas.hansson@arm.com}}; 2129293Sandreas.hansson@arm.com 2139293Sandreas.hansson@arm.comdef format MT_MTTR(code, *flags) {{ 2149293Sandreas.hansson@arm.com flags += ('IsNonSpeculative', ) 2159293Sandreas.hansson@arm.com# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2169293Sandreas.hansson@arm.com iop = InstObjParams(name, Name, 'MTOp', code, flags) 2179293Sandreas.hansson@arm.com header_output = BasicDeclare.subst(iop) 2189293Sandreas.hansson@arm.com decoder_output = BasicConstructor.subst(iop) 2199293Sandreas.hansson@arm.com decode_block = BasicDecode.subst(iop) 2209293Sandreas.hansson@arm.com exec_output = ThreadRegisterExecute.subst(iop) 2219293Sandreas.hansson@arm.com}}; 2229293Sandreas.hansson@arm.com