mt.isa revision 13899
12440SN/A// -*- mode:c++ -*- 22440SN/A 32440SN/A// Copyright (c) 2007 MIPS Technologies, Inc. 42440SN/A// All rights reserved. 52440SN/A// 62440SN/A// Redistribution and use in source and binary forms, with or without 72440SN/A// modification, are permitted provided that the following conditions are 82440SN/A// met: redistributions of source code must retain the above copyright 92440SN/A// notice, this list of conditions and the following disclaimer; 102440SN/A// redistributions in binary form must reproduce the above copyright 112440SN/A// notice, this list of conditions and the following disclaimer in the 122440SN/A// documentation and/or other materials provided with the distribution; 132440SN/A// neither the name of the copyright holders nor the names of its 142440SN/A// contributors may be used to endorse or promote products derived from 152440SN/A// this software without specific prior written permission. 162440SN/A// 172440SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182440SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192440SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202440SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212440SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222440SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232440SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242440SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252440SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262440SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Korey Sewell 302440SN/A 312440SN/A//////////////////////////////////////////////////////////////////// 322440SN/A// 332440SN/A// MT instructions 342440SN/A// 352440SN/A 362440SN/Aoutput header {{ 372972Sgblack@eecs.umich.edu /** 382460SN/A * Base class for MIPS MT ASE operations. 392440SN/A */ 403120Sgblack@eecs.umich.edu class MTOp : public MipsStaticInst 412440SN/A { 422440SN/A protected: 432440SN/A 442440SN/A /// Constructor 454826Ssaidi@eecs.umich.edu MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 464826Ssaidi@eecs.umich.edu MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 473577Sgblack@eecs.umich.edu { 483577Sgblack@eecs.umich.edu } 493577Sgblack@eecs.umich.edu 504172Ssaidi@eecs.umich.edu std::string generateDisassembly( 513577Sgblack@eecs.umich.edu Addr pc, const SymbolTable *symtab) const override; 523577Sgblack@eecs.umich.edu 532467SN/A bool user_mode; 542440SN/A }; 552440SN/A 562440SN/A class MTUserModeOp : public MTOp 572440SN/A { 582467SN/A protected: 592440SN/A 602440SN/A /// Constructor 612440SN/A MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 622440SN/A MTOp(mnem, _machInst, __opClass) 632467SN/A { 642440SN/A user_mode = true; 652440SN/A } 662440SN/A }; 672440SN/A}}; 682467SN/A 692440SN/Aoutput decoder {{ 702440SN/A std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 712440SN/A { 722440SN/A std::stringstream ss; 732467SN/A 742440SN/A if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) { 752440SN/A ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 762440SN/A } else if (strcmp(mnemonic,"mftgpr") == 0) { 772440SN/A ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 782440SN/A } else { 792467SN/A ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 802440SN/A } 812440SN/A 822440SN/A return ss.str(); 832467SN/A } 842440SN/A}}; 852440SN/A 862440SN/Aoutput header {{ 872440SN/A void getThrRegExValues(ExecContext *xc, 882440SN/A MipsISA::VPEConf0Reg &vpe_conf0, 892467SN/A MipsISA::TCBindReg &tc_bind_mt, 902440SN/A MipsISA::TCBindReg &tc_bind, 912440SN/A MipsISA::VPEControlReg &vpe_control, 922440SN/A MipsISA::MVPConf0Reg &mvp_conf0); 932467SN/A 942440SN/A void getMTExValues(ExecContext *xc, MipsISA::Config3Reg &config3); 952440SN/A}}; 962440SN/A 972440SN/Aoutput exec {{ 982440SN/A void getThrRegExValues(ExecContext *xc, 992440SN/A VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt, 1002440SN/A TCBindReg &tc_bind, VPEControlReg &vpe_control, 1012440SN/A MVPConf0Reg &mvp_conf0) 1022440SN/A { 1032440SN/A vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); 1042440SN/A tc_bind_mt = readRegOtherThread(xc, RegId(MiscRegClass, 1052440SN/A MISCREG_TC_BIND)); 1062440SN/A tc_bind = xc->readMiscReg(MISCREG_TC_BIND); 1072440SN/A vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); 1082680Sktlim@umich.edu mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); 1092440SN/A } 1102680Sktlim@umich.edu 1112680Sktlim@umich.edu void getMTExValues(ExecContext *xc, Config3Reg &config3) 1122440SN/A { 1133961Sgblack@eecs.umich.edu config3 = xc->readMiscReg(MISCREG_CONFIG3); 1143961Sgblack@eecs.umich.edu } 1154194Ssaidi@eecs.umich.edu}}; 1164194Ssaidi@eecs.umich.edu 1174194Ssaidi@eecs.umich.edudef template ThreadRegisterExecute {{ 1182440SN/A Fault %(class_name)s::execute( 1192440SN/A ExecContext *xc, Trace::InstRecord *traceData) const 1202440SN/A { 1212440SN/A Fault fault = NoFault; 1222440SN/A int64_t data M5_VAR_USED; 1232440SN/A %(op_decl)s; 1242440SN/A %(op_rd)s; 1252467SN/A 1262440SN/A VPEConf0Reg vpeConf0; 1272440SN/A TCBindReg tcBindMT; 1282467SN/A TCBindReg tcBind; 1292440SN/A VPEControlReg vpeControl; 1302440SN/A MVPConf0Reg mvpConf0; 1312467SN/A 1322467SN/A getThrRegExValues(xc, vpeConf0, tcBindMT, 1332440SN/A tcBind, vpeControl, mvpConf0); 1342440SN/A 1352467SN/A if (isCoprocessorEnabled(xc, 0)) { 1362440SN/A if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) { 1372467SN/A data = -1; 1382440SN/A } else if (vpeControl.targTC > mvpConf0.ptc) { 1392440SN/A data = -1; 1402440SN/A } else { 1412467SN/A %(code)s; 1422440SN/A } 1432440SN/A } else { 1442440SN/A fault = std::make_shared<CoprocessorUnusableFault>(0); 1452680Sktlim@umich.edu } 1462680Sktlim@umich.edu 1472440SN/A if(fault == NoFault) 1482440SN/A { 1492440SN/A %(op_wb)s; 1502680Sktlim@umich.edu } 1512440SN/A 1522680Sktlim@umich.edu return fault; 1532680Sktlim@umich.edu } 1542440SN/A}}; 1552440SN/A 1562440SN/Adef template MTExecute{{ 1572440SN/A Fault %(class_name)s::execute( 1582440SN/A ExecContext *xc, Trace::InstRecord *traceData) const 159 { 160 Fault fault = NoFault; 161 %(op_decl)s; 162 %(op_rd)s; 163 164 Config3Reg config3; 165 166 getMTExValues(xc, config3); 167 168 if (isCoprocessorEnabled(xc, 0)) { 169 if (config3.mt == 1) { 170 %(code)s; 171 } else { 172 fault = std::make_shared<ReservedInstructionFault>(); 173 } 174 } else { 175 fault = std::make_shared<CoprocessorUnusableFault>(0); 176 } 177 178 if(fault == NoFault) 179 { 180 %(op_wb)s; 181 } 182 return fault; 183 } 184}}; 185 186// Primary format for integer operate instructions: 187def format MT_Control(code, *opt_flags) {{ 188 inst_flags = ('IsNonSpeculative', ) 189 op_type = 'MTOp' 190 191 for x in opt_flags: 192 if x == 'UserMode': 193 op_type = 'MTUserModeOp' 194 else: 195 inst_flags += (x, ) 196 197 iop = InstObjParams(name, Name, op_type, code, inst_flags) 198 header_output = BasicDeclare.subst(iop) 199 decoder_output = BasicConstructor.subst(iop) 200 decode_block = BasicDecode.subst(iop) 201 exec_output = MTExecute.subst(iop) 202}}; 203 204def format MT_MFTR(code, *flags) {{ 205 flags += ('IsNonSpeculative', ) 206# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 207 208 code += ''' 209 if (MT_H) 210 data = bits(data, 63, 32); 211 Rd = data; 212 ''' 213 214 iop = InstObjParams(name, Name, 'MTOp', code, flags) 215 header_output = BasicDeclare.subst(iop) 216 decoder_output = BasicConstructor.subst(iop) 217 decode_block = BasicDecode.subst(iop) 218 exec_output = ThreadRegisterExecute.subst(iop) 219}}; 220 221def format MT_MTTR(code, *flags) {{ 222 flags += ('IsNonSpeculative', ) 223# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 224 iop = InstObjParams(name, Name, 'MTOp', code, flags) 225 header_output = BasicDeclare.subst(iop) 226 decoder_output = BasicConstructor.subst(iop) 227 decode_block = BasicDecode.subst(iop) 228 exec_output = ThreadRegisterExecute.subst(iop) 229}}; 230