mt.isa revision 12616
12686Sksewell@umich.edu// -*- mode:c++ -*- 22686Sksewell@umich.edu 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Korey Sewell 302706Sksewell@umich.edu 312686Sksewell@umich.edu//////////////////////////////////////////////////////////////////// 322686Sksewell@umich.edu// 332686Sksewell@umich.edu// MT instructions 342686Sksewell@umich.edu// 352686Sksewell@umich.edu 362686Sksewell@umich.eduoutput header {{ 372686Sksewell@umich.edu /** 382741Sksewell@umich.edu * Base class for MIPS MT ASE operations. 392686Sksewell@umich.edu */ 404661Sksewell@umich.edu class MTOp : public MipsStaticInst 412686Sksewell@umich.edu { 422686Sksewell@umich.edu protected: 432686Sksewell@umich.edu 442686Sksewell@umich.edu /// Constructor 454661Sksewell@umich.edu MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 464661Sksewell@umich.edu MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 472686Sksewell@umich.edu { 482686Sksewell@umich.edu } 492686Sksewell@umich.edu 5012616Sgabeblack@google.com std::string generateDisassembly( 5112616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 524661Sksewell@umich.edu 534661Sksewell@umich.edu bool user_mode; 544661Sksewell@umich.edu }; 554661Sksewell@umich.edu 564661Sksewell@umich.edu class MTUserModeOp : public MTOp 574661Sksewell@umich.edu { 584661Sksewell@umich.edu protected: 594661Sksewell@umich.edu 604661Sksewell@umich.edu /// Constructor 614661Sksewell@umich.edu MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 624661Sksewell@umich.edu MTOp(mnem, _machInst, __opClass) 634661Sksewell@umich.edu { 644661Sksewell@umich.edu user_mode = true; 654661Sksewell@umich.edu } 662686Sksewell@umich.edu }; 672686Sksewell@umich.edu}}; 682686Sksewell@umich.edu 692686Sksewell@umich.eduoutput decoder {{ 704661Sksewell@umich.edu std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 714661Sksewell@umich.edu { 724661Sksewell@umich.edu std::stringstream ss; 734661Sksewell@umich.edu 745269Sksewell@umich.edu if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) { 754661Sksewell@umich.edu ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 765269Sksewell@umich.edu } else if (strcmp(mnemonic,"mftgpr") == 0) { 774661Sksewell@umich.edu ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 784661Sksewell@umich.edu } else { 794661Sksewell@umich.edu ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 804661Sksewell@umich.edu } 814661Sksewell@umich.edu 824661Sksewell@umich.edu return ss.str(); 834661Sksewell@umich.edu } 844661Sksewell@umich.edu}}; 854661Sksewell@umich.edu 869554Sandreas.hansson@arm.comoutput header {{ 8712234Sgabeblack@google.com void getThrRegExValues(ExecContext *xc, 889554Sandreas.hansson@arm.com MipsISA::VPEConf0Reg &vpe_conf0, 899554Sandreas.hansson@arm.com MipsISA::TCBindReg &tc_bind_mt, 909554Sandreas.hansson@arm.com MipsISA::TCBindReg &tc_bind, 919554Sandreas.hansson@arm.com MipsISA::VPEControlReg &vpe_control, 929554Sandreas.hansson@arm.com MipsISA::MVPConf0Reg &mvp_conf0); 939554Sandreas.hansson@arm.com 9412234Sgabeblack@google.com void getMTExValues(ExecContext *xc, MipsISA::Config3Reg &config3); 959554Sandreas.hansson@arm.com}}; 969554Sandreas.hansson@arm.com 974661Sksewell@umich.eduoutput exec {{ 9812234Sgabeblack@google.com void getThrRegExValues(ExecContext *xc, 996376Sgblack@eecs.umich.edu VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt, 1006376Sgblack@eecs.umich.edu TCBindReg &tc_bind, VPEControlReg &vpe_control, 1016376Sgblack@eecs.umich.edu MVPConf0Reg &mvp_conf0) 1024661Sksewell@umich.edu { 1036383Sgblack@eecs.umich.edu vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); 10412104Snathanael.premillieu@arm.com tc_bind_mt = xc->readRegOtherThread(RegId(MiscRegClass, 10512104Snathanael.premillieu@arm.com MISCREG_TC_BIND)); 1066383Sgblack@eecs.umich.edu tc_bind = xc->readMiscReg(MISCREG_TC_BIND); 1076383Sgblack@eecs.umich.edu vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); 1086383Sgblack@eecs.umich.edu mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); 1094661Sksewell@umich.edu } 1104661Sksewell@umich.edu 11112234Sgabeblack@google.com void getMTExValues(ExecContext *xc, Config3Reg &config3) 1124661Sksewell@umich.edu { 1136383Sgblack@eecs.umich.edu config3 = xc->readMiscReg(MISCREG_CONFIG3); 1144661Sksewell@umich.edu } 1154661Sksewell@umich.edu}}; 1164661Sksewell@umich.edu 1174661Sksewell@umich.edudef template ThreadRegisterExecute {{ 11812234Sgabeblack@google.com Fault %(class_name)s::execute( 11912234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 1202686Sksewell@umich.edu { 1214661Sksewell@umich.edu Fault fault = NoFault; 1228607Sgblack@eecs.umich.edu int64_t data M5_VAR_USED; 1234661Sksewell@umich.edu %(op_decl)s; 1244661Sksewell@umich.edu %(op_rd)s; 1254661Sksewell@umich.edu 1266376Sgblack@eecs.umich.edu VPEConf0Reg vpeConf0; 1276376Sgblack@eecs.umich.edu TCBindReg tcBindMT; 1286376Sgblack@eecs.umich.edu TCBindReg tcBind; 1296376Sgblack@eecs.umich.edu VPEControlReg vpeControl; 1306376Sgblack@eecs.umich.edu MVPConf0Reg mvpConf0; 1314661Sksewell@umich.edu 1326376Sgblack@eecs.umich.edu getThrRegExValues(xc, vpeConf0, tcBindMT, 1336376Sgblack@eecs.umich.edu tcBind, vpeControl, mvpConf0); 1344661Sksewell@umich.edu 1354661Sksewell@umich.edu if (isCoprocessorEnabled(xc, 0)) { 1366376Sgblack@eecs.umich.edu if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) { 1374661Sksewell@umich.edu data = -1; 1386376Sgblack@eecs.umich.edu } else if (vpeControl.targTC > mvpConf0.ptc) { 1394661Sksewell@umich.edu data = -1; 1404661Sksewell@umich.edu } else { 1414661Sksewell@umich.edu %(code)s; 1424661Sksewell@umich.edu } 1434661Sksewell@umich.edu } else { 14410474Sandreas.hansson@arm.com fault = std::make_shared<CoprocessorUnusableFault>(0); 1454661Sksewell@umich.edu } 1464661Sksewell@umich.edu 1474661Sksewell@umich.edu if(fault == NoFault) 1484661Sksewell@umich.edu { 1494661Sksewell@umich.edu %(op_wb)s; 1504661Sksewell@umich.edu } 1514661Sksewell@umich.edu 1524661Sksewell@umich.edu return fault; 1532686Sksewell@umich.edu } 1542686Sksewell@umich.edu}}; 1552686Sksewell@umich.edu 1564661Sksewell@umich.edudef template MTExecute{{ 15712234Sgabeblack@google.com Fault %(class_name)s::execute( 15812234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 1592686Sksewell@umich.edu { 1604661Sksewell@umich.edu Fault fault = NoFault; 1614661Sksewell@umich.edu %(op_decl)s; 1624661Sksewell@umich.edu %(op_rd)s; 1632686Sksewell@umich.edu 1646376Sgblack@eecs.umich.edu Config3Reg config3; 1654661Sksewell@umich.edu 1664661Sksewell@umich.edu getMTExValues(xc, config3); 1674661Sksewell@umich.edu 1684661Sksewell@umich.edu if (isCoprocessorEnabled(xc, 0)) { 1696376Sgblack@eecs.umich.edu if (config3.mt == 1) { 1704661Sksewell@umich.edu %(code)s; 1714661Sksewell@umich.edu } else { 17210474Sandreas.hansson@arm.com fault = std::make_shared<ReservedInstructionFault>(); 1734661Sksewell@umich.edu } 1744661Sksewell@umich.edu } else { 17510474Sandreas.hansson@arm.com fault = std::make_shared<CoprocessorUnusableFault>(0); 1764661Sksewell@umich.edu } 1774661Sksewell@umich.edu 1784661Sksewell@umich.edu if(fault == NoFault) 1794661Sksewell@umich.edu { 1804661Sksewell@umich.edu %(op_wb)s; 1814661Sksewell@umich.edu } 1824661Sksewell@umich.edu return fault; 1832686Sksewell@umich.edu } 1842686Sksewell@umich.edu}}; 1852686Sksewell@umich.edu 1862686Sksewell@umich.edu// Primary format for integer operate instructions: 1874661Sksewell@umich.edudef format MT_Control(code, *opt_flags) {{ 1884661Sksewell@umich.edu inst_flags = ('IsNonSpeculative', ) 1894661Sksewell@umich.edu op_type = 'MTOp' 1904661Sksewell@umich.edu 1914661Sksewell@umich.edu for x in opt_flags: 1924661Sksewell@umich.edu if x == 'UserMode': 1934661Sksewell@umich.edu op_type = 'MTUserModeOp' 1944661Sksewell@umich.edu else: 1954661Sksewell@umich.edu inst_flags += (x, ) 1964661Sksewell@umich.edu 1974661Sksewell@umich.edu iop = InstObjParams(name, Name, op_type, code, inst_flags) 1982686Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 1992686Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2002686Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2014661Sksewell@umich.edu exec_output = MTExecute.subst(iop) 2022686Sksewell@umich.edu}}; 2034661Sksewell@umich.edu 2044661Sksewell@umich.edudef format MT_MFTR(code, *flags) {{ 2054661Sksewell@umich.edu flags += ('IsNonSpeculative', ) 2067823Ssteve.reinhardt@amd.com# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2074661Sksewell@umich.edu 2088607Sgblack@eecs.umich.edu code += ''' 2098607Sgblack@eecs.umich.edu if (MT_H) 2108607Sgblack@eecs.umich.edu data = bits(data, 63, 32); 2118607Sgblack@eecs.umich.edu Rd = data; 2128607Sgblack@eecs.umich.edu ''' 2134661Sksewell@umich.edu 2144661Sksewell@umich.edu iop = InstObjParams(name, Name, 'MTOp', code, flags) 2154661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2164661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2174661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2184661Sksewell@umich.edu exec_output = ThreadRegisterExecute.subst(iop) 2194661Sksewell@umich.edu}}; 2204661Sksewell@umich.edu 2214661Sksewell@umich.edudef format MT_MTTR(code, *flags) {{ 2224661Sksewell@umich.edu flags += ('IsNonSpeculative', ) 2237823Ssteve.reinhardt@amd.com# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2244661Sksewell@umich.edu iop = InstObjParams(name, Name, 'MTOp', code, flags) 2254661Sksewell@umich.edu header_output = BasicDeclare.subst(iop) 2264661Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 2274661Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 2284661Sksewell@umich.edu exec_output = ThreadRegisterExecute.subst(iop) 2294661Sksewell@umich.edu}}; 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