mt.isa revision 10474
11758SN/A// -*- mode:c++ -*- 21762SN/A 31758SN/A// Copyright (c) 2007 MIPS Technologies, Inc. 41758SN/A// All rights reserved. 51758SN/A// 61758SN/A// Redistribution and use in source and binary forms, with or without 71758SN/A// modification, are permitted provided that the following conditions are 81758SN/A// met: redistributions of source code must retain the above copyright 91758SN/A// notice, this list of conditions and the following disclaimer; 101758SN/A// redistributions in binary form must reproduce the above copyright 111758SN/A// notice, this list of conditions and the following disclaimer in the 121758SN/A// documentation and/or other materials provided with the distribution; 131758SN/A// neither the name of the copyright holders nor the names of its 141758SN/A// contributors may be used to endorse or promote products derived from 151758SN/A// this software without specific prior written permission. 161758SN/A// 171758SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181758SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191758SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201758SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211758SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221758SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231758SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241758SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251758SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261758SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Korey Sewell 302665Ssaidi@eecs.umich.edu 311758SN/A//////////////////////////////////////////////////////////////////// 322SN/A// 331147SN/A// MT instructions 341147SN/A// 352SN/A 361858SN/Aoutput header {{ 372107SN/A /** 381858SN/A * Base class for MIPS MT ASE operations. 395566Snate@binkert.org */ 402107SN/A class MTOp : public MipsStaticInst 411858SN/A { 421147SN/A protected: 43924SN/A 441147SN/A /// Constructor 45924SN/A MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 46924SN/A MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 471147SN/A { 481147SN/A } 491147SN/A 501147SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 511147SN/A 521147SN/A bool user_mode; 531147SN/A }; 541147SN/A 55924SN/A class MTUserModeOp : public MTOp 561858SN/A { 571147SN/A protected: 581147SN/A 59924SN/A /// Constructor 601147SN/A MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 611147SN/A MTOp(mnem, _machInst, __opClass) 62924SN/A { 631147SN/A user_mode = true; 641147SN/A } 651147SN/A 661147SN/A //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 671147SN/A }; 681805SN/A}}; 691805SN/A 701858SN/Aoutput decoder {{ 711805SN/A std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 721805SN/A { 731805SN/A std::stringstream ss; 741805SN/A 751805SN/A if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) { 761805SN/A ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 771805SN/A } else if (strcmp(mnemonic,"mftgpr") == 0) { 78924SN/A ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 791147SN/A } else { 801147SN/A ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 811147SN/A } 821147SN/A 831147SN/A return ss.str(); 841147SN/A } 851147SN/A}}; 861147SN/A 871147SN/Aoutput header {{ 882SN/A void getThrRegExValues(%(CPU_exec_context)s *xc, 891147SN/A MipsISA::VPEConf0Reg &vpe_conf0, 901147SN/A MipsISA::TCBindReg &tc_bind_mt, 911147SN/A MipsISA::TCBindReg &tc_bind, 921147SN/A MipsISA::VPEControlReg &vpe_control, 931147SN/A MipsISA::MVPConf0Reg &mvp_conf0); 941147SN/A 951147SN/A void getMTExValues(%(CPU_exec_context)s *xc, MipsISA::Config3Reg &config3); 961147SN/A}}; 972SN/A 981147SN/Aoutput exec {{ 992SN/A void getThrRegExValues(CPU_EXEC_CONTEXT *xc, 1001147SN/A VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt, 1011147SN/A TCBindReg &tc_bind, VPEControlReg &vpe_control, 1021147SN/A MVPConf0Reg &mvp_conf0) 1032SN/A { 1041147SN/A vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); 1051147SN/A tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base); 1061147SN/A tc_bind = xc->readMiscReg(MISCREG_TC_BIND); 1072SN/A vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); 1081147SN/A mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); 1091147SN/A } 1101147SN/A 1111147SN/A void getMTExValues(CPU_EXEC_CONTEXT *xc, Config3Reg &config3) 1121147SN/A { 1131147SN/A config3 = xc->readMiscReg(MISCREG_CONFIG3); 1141147SN/A } 1151147SN/A}}; 1162SN/A 1171147SN/Adef template ThreadRegisterExecute {{ 1181147SN/A Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 1192SN/A { 1205566Snate@binkert.org Fault fault = NoFault; 1212SN/A int64_t data M5_VAR_USED; 1221147SN/A %(op_decl)s; 123 %(op_rd)s; 124 125 VPEConf0Reg vpeConf0; 126 TCBindReg tcBindMT; 127 TCBindReg tcBind; 128 VPEControlReg vpeControl; 129 MVPConf0Reg mvpConf0; 130 131 getThrRegExValues(xc, vpeConf0, tcBindMT, 132 tcBind, vpeControl, mvpConf0); 133 134 if (isCoprocessorEnabled(xc, 0)) { 135 if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) { 136 data = -1; 137 } else if (vpeControl.targTC > mvpConf0.ptc) { 138 data = -1; 139 } else { 140 %(code)s; 141 } 142 } else { 143 fault = std::make_shared<CoprocessorUnusableFault>(0); 144 } 145 146 if(fault == NoFault) 147 { 148 %(op_wb)s; 149 } 150 151 return fault; 152 } 153}}; 154 155def template MTExecute{{ 156 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 157 { 158 Fault fault = NoFault; 159 %(op_decl)s; 160 %(op_rd)s; 161 162 Config3Reg config3; 163 164 getMTExValues(xc, config3); 165 166 if (isCoprocessorEnabled(xc, 0)) { 167 if (config3.mt == 1) { 168 %(code)s; 169 } else { 170 fault = std::make_shared<ReservedInstructionFault>(); 171 } 172 } else { 173 fault = std::make_shared<CoprocessorUnusableFault>(0); 174 } 175 176 if(fault == NoFault) 177 { 178 %(op_wb)s; 179 } 180 return fault; 181 } 182}}; 183 184// Primary format for integer operate instructions: 185def format MT_Control(code, *opt_flags) {{ 186 inst_flags = ('IsNonSpeculative', ) 187 op_type = 'MTOp' 188 189 for x in opt_flags: 190 if x == 'UserMode': 191 op_type = 'MTUserModeOp' 192 else: 193 inst_flags += (x, ) 194 195 iop = InstObjParams(name, Name, op_type, code, inst_flags) 196 header_output = BasicDeclare.subst(iop) 197 decoder_output = BasicConstructor.subst(iop) 198 decode_block = BasicDecode.subst(iop) 199 exec_output = MTExecute.subst(iop) 200}}; 201 202def format MT_MFTR(code, *flags) {{ 203 flags += ('IsNonSpeculative', ) 204# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 205 206 code += ''' 207 if (MT_H) 208 data = bits(data, 63, 32); 209 Rd = data; 210 ''' 211 212 iop = InstObjParams(name, Name, 'MTOp', code, flags) 213 header_output = BasicDeclare.subst(iop) 214 decoder_output = BasicConstructor.subst(iop) 215 decode_block = BasicDecode.subst(iop) 216 exec_output = ThreadRegisterExecute.subst(iop) 217}}; 218 219def format MT_MTTR(code, *flags) {{ 220 flags += ('IsNonSpeculative', ) 221# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 222 iop = InstObjParams(name, Name, 'MTOp', code, flags) 223 header_output = BasicDeclare.subst(iop) 224 decoder_output = BasicConstructor.subst(iop) 225 decode_block = BasicDecode.subst(iop) 226 exec_output = ThreadRegisterExecute.subst(iop) 227}}; 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