mem.isa revision 7045:e21fe6a62b1c
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Steve Reinhardt 30// Korey Sewell 31 32//////////////////////////////////////////////////////////////////// 33// 34// Memory-format instructions 35// 36 37output header {{ 38 /** 39 * Base class for general Mips memory-format instructions. 40 */ 41 class Memory : public MipsStaticInst 42 { 43 protected: 44 /// Memory request flags. See mem_req_base.hh. 45 Request::Flags memAccessFlags; 46 47 /// Displacement for EA calculation (signed). 48 int32_t disp; 49 50 /// Constructor 51 Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 52 : MipsStaticInst(mnem, _machInst, __opClass), 53 disp(sext<16>(OFFSET)) 54 { 55 } 56 57 std::string 58 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 59 }; 60 61 /** 62 * Base class for a few miscellaneous memory-format insts 63 * that don't interpret the disp field 64 */ 65 class MemoryNoDisp : public Memory 66 { 67 protected: 68 /// Constructor 69 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 70 : Memory(mnem, _machInst, __opClass) 71 { 72 } 73 74 std::string 75 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 76 }; 77}}; 78 79 80output decoder {{ 81 std::string 82 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 83 { 84 return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 85 flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 86 } 87 88 std::string 89 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 90 { 91 return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 92 flags[IsFloating] ? 'f' : 'r', 93 flags[IsFloating] ? FD : RD, 94 RS, RT); 95 } 96 97}}; 98 99output exec {{ 100 /** return data in cases where there the size of data is only 101 known in the packet 102 */ 103 uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) { 104 switch (packet->getSize()) 105 { 106 case 1: 107 return packet->get<uint8_t>(); 108 109 case 2: 110 return packet->get<uint16_t>(); 111 112 case 4: 113 return packet->get<uint32_t>(); 114 115 case 8: 116 return packet->get<uint64_t>(); 117 118 default: 119 std::cerr << "bad store data size = " << packet->getSize() << std::endl; 120 121 assert(0); 122 return 0; 123 } 124 } 125 126 127}}; 128 129def template LoadStoreDeclare {{ 130 /** 131 * Static instruction class for "%(mnemonic)s". 132 */ 133 class %(class_name)s : public %(base_class)s 134 { 135 public: 136 137 /// Constructor. 138 %(class_name)s(ExtMachInst machInst); 139 140 %(BasicExecDeclare)s 141 142 %(EACompDeclare)s 143 144 %(InitiateAccDeclare)s 145 146 %(CompleteAccDeclare)s 147 }; 148}}; 149 150def template EACompDeclare {{ 151 Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 152}}; 153 154def template InitiateAccDeclare {{ 155 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 156}}; 157 158 159def template CompleteAccDeclare {{ 160 Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 161}}; 162 163def template LoadStoreConstructor {{ 164 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 165 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 166 { 167 %(constructor)s; 168 } 169}}; 170 171 172def template EACompExecute {{ 173 Fault 174 %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 175 Trace::InstRecord *traceData) const 176 { 177 Addr EA; 178 Fault fault = NoFault; 179 180 if (this->isFloating()) { 181 %(fp_enable_check)s; 182 183 if(fault != NoFault) 184 return fault; 185 } 186 187 %(op_decl)s; 188 %(op_rd)s; 189 %(ea_code)s; 190 191 // NOTE: Trace Data is written using execute or completeAcc templates 192 if (fault == NoFault) { 193 xc->setEA(EA); 194 } 195 196 return fault; 197 } 198}}; 199 200def template LoadExecute {{ 201 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 202 Trace::InstRecord *traceData) const 203 { 204 Addr EA; 205 Fault fault = NoFault; 206 207 if (this->isFloating()) { 208 %(fp_enable_check)s; 209 210 if(fault != NoFault) 211 return fault; 212 } 213 214 %(op_decl)s; 215 %(op_rd)s; 216 %(ea_code)s; 217 218 if (fault == NoFault) { 219 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 220 %(memacc_code)s; 221 } 222 223 if (fault == NoFault) { 224 %(op_wb)s; 225 } 226 227 return fault; 228 } 229}}; 230 231 232def template LoadInitiateAcc {{ 233 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 234 Trace::InstRecord *traceData) const 235 { 236 Addr EA; 237 Fault fault = NoFault; 238 239 if (this->isFloating()) { 240 %(fp_enable_check)s; 241 242 if(fault != NoFault) 243 return fault; 244 } 245 246 %(op_src_decl)s; 247 %(op_rd)s; 248 %(ea_code)s; 249 250 if (fault == NoFault) { 251 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 252 } 253 254 return fault; 255 } 256}}; 257 258def template LoadCompleteAcc {{ 259 Fault %(class_name)s::completeAcc(Packet *pkt, 260 %(CPU_exec_context)s *xc, 261 Trace::InstRecord *traceData) const 262 { 263 Fault fault = NoFault; 264 265 if (this->isFloating()) { 266 %(fp_enable_check)s; 267 268 if(fault != NoFault) 269 return fault; 270 } 271 272 %(op_decl)s; 273 %(op_rd)s; 274 275 Mem = pkt->get<typeof(Mem)>(); 276 277 if (fault == NoFault) { 278 %(memacc_code)s; 279 } 280 281 if (fault == NoFault) { 282 %(op_wb)s; 283 } 284 285 return fault; 286 } 287}}; 288 289def template StoreExecute {{ 290 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 291 Trace::InstRecord *traceData) const 292 { 293 Addr EA; 294 Fault fault = NoFault; 295 296 %(fp_enable_check)s; 297 %(op_decl)s; 298 %(op_rd)s; 299 %(ea_code)s; 300 301 if (fault == NoFault) { 302 %(memacc_code)s; 303 } 304 305 if (fault == NoFault) { 306 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 307 memAccessFlags, NULL); 308 } 309 310 if (fault == NoFault) { 311 %(postacc_code)s; 312 } 313 314 if (fault == NoFault) { 315 %(op_wb)s; 316 } 317 318 return fault; 319 } 320}}; 321 322 323def template StoreFPExecute {{ 324 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 325 Trace::InstRecord *traceData) const 326 { 327 Addr EA; 328 Fault fault = NoFault; 329 330 %(fp_enable_check)s; 331 if(fault != NoFault) 332 return fault; 333 %(op_decl)s; 334 %(op_rd)s; 335 %(ea_code)s; 336 337 if (fault == NoFault) { 338 %(memacc_code)s; 339 } 340 341 if (fault == NoFault) { 342 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 343 memAccessFlags, NULL); 344 } 345 346 if (fault == NoFault) { 347 %(postacc_code)s; 348 } 349 350 if (fault == NoFault) { 351 %(op_wb)s; 352 } 353 354 return fault; 355 } 356}}; 357 358def template StoreCondExecute {{ 359 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 360 Trace::InstRecord *traceData) const 361 { 362 Addr EA; 363 Fault fault = NoFault; 364 uint64_t write_result = 0; 365 366 %(fp_enable_check)s; 367 %(op_decl)s; 368 %(op_rd)s; 369 %(ea_code)s; 370 371 if (fault == NoFault) { 372 %(memacc_code)s; 373 } 374 375 if (fault == NoFault) { 376 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 377 memAccessFlags, &write_result); 378 } 379 380 if (fault == NoFault) { 381 %(postacc_code)s; 382 } 383 384 if (fault == NoFault) { 385 %(op_wb)s; 386 } 387 388 return fault; 389 } 390}}; 391 392def template StoreInitiateAcc {{ 393 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 394 Trace::InstRecord *traceData) const 395 { 396 Addr EA; 397 Fault fault = NoFault; 398 399 %(fp_enable_check)s; 400 %(op_decl)s; 401 %(op_rd)s; 402 %(ea_code)s; 403 404 if (fault == NoFault) { 405 %(memacc_code)s; 406 } 407 408 if (fault == NoFault) { 409 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 410 memAccessFlags, NULL); 411 } 412 413 return fault; 414 } 415}}; 416 417 418def template StoreCompleteAcc {{ 419 Fault %(class_name)s::completeAcc(Packet *pkt, 420 %(CPU_exec_context)s *xc, 421 Trace::InstRecord *traceData) const 422 { 423 Fault fault = NoFault; 424 425 %(fp_enable_check)s; 426 %(op_dest_decl)s; 427 428 if (fault == NoFault) { 429 %(postacc_code)s; 430 } 431 432 if (fault == NoFault) { 433 %(op_wb)s; 434 } 435 436 return fault; 437 } 438}}; 439 440 441def template StoreCompleteAcc {{ 442 Fault %(class_name)s::completeAcc(Packet *pkt, 443 %(CPU_exec_context)s *xc, 444 Trace::InstRecord *traceData) const 445 { 446 Fault fault = NoFault; 447 448 %(op_dest_decl)s; 449 450 if (fault == NoFault) { 451 %(postacc_code)s; 452 } 453 454 if (fault == NoFault) { 455 %(op_wb)s; 456 } 457 458 return fault; 459 } 460}}; 461 462def template StoreCondCompleteAcc {{ 463 Fault %(class_name)s::completeAcc(Packet *pkt, 464 %(CPU_exec_context)s *xc, 465 Trace::InstRecord *traceData) const 466 { 467 Fault fault = NoFault; 468 469 %(fp_enable_check)s; 470 %(op_dest_decl)s; 471 472 uint64_t write_result = pkt->req->getExtraData(); 473 474 if (fault == NoFault) { 475 %(postacc_code)s; 476 } 477 478 if (fault == NoFault) { 479 %(op_wb)s; 480 } 481 482 return fault; 483 } 484}}; 485 486def template MiscExecute {{ 487 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 488 Trace::InstRecord *traceData) const 489 { 490 Addr EA; 491 Fault fault = NoFault; 492 493 %(fp_enable_check)s; 494 %(op_decl)s; 495 %(op_rd)s; 496 %(ea_code)s; 497 498 if (fault == NoFault) { 499 %(memacc_code)s; 500 } 501 502 return NoFault; 503 } 504}}; 505 506def template MiscInitiateAcc {{ 507 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 508 Trace::InstRecord *traceData) const 509 { 510 panic("Misc instruction does not support split access method!"); 511 return NoFault; 512 } 513}}; 514 515 516def template MiscCompleteAcc {{ 517 Fault %(class_name)s::completeAcc(Packet *pkt, 518 %(CPU_exec_context)s *xc, 519 Trace::InstRecord *traceData) const 520 { 521 panic("Misc instruction does not support split access method!"); 522 523 return NoFault; 524 } 525}}; 526 527def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 528 mem_flags = [], inst_flags = []) {{ 529 (header_output, decoder_output, decode_block, exec_output) = \ 530 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 531 decode_template = ImmNopCheckDecode, 532 exec_template_base = 'Load') 533}}; 534 535 536def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 537 mem_flags = [], inst_flags = []) {{ 538 (header_output, decoder_output, decode_block, exec_output) = \ 539 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 540 exec_template_base = 'Store') 541}}; 542 543def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 544 mem_flags = [], inst_flags = []) {{ 545 inst_flags += ['IsIndexed'] 546 (header_output, decoder_output, decode_block, exec_output) = \ 547 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 548 decode_template = ImmNopCheckDecode, 549 exec_template_base = 'Load') 550}}; 551 552def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 553 mem_flags = [], inst_flags = []) {{ 554 inst_flags += ['IsIndexed'] 555 (header_output, decoder_output, decode_block, exec_output) = \ 556 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 557 exec_template_base = 'Store') 558}}; 559 560def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 561 mem_flags = [], inst_flags = []) {{ 562 inst_flags += ['IsIndexed', 'IsFloating'] 563 (header_output, decoder_output, decode_block, exec_output) = \ 564 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 565 decode_template = ImmNopCheckDecode, 566 exec_template_base = 'Load') 567}}; 568 569def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 570 mem_flags = [], inst_flags = []) {{ 571 inst_flags += ['IsIndexed', 'IsFloating'] 572 (header_output, decoder_output, decode_block, exec_output) = \ 573 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 574 exec_template_base = 'Store') 575}}; 576 577 578def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 579 mem_flags = [], inst_flags = []) {{ 580 decl_code = 'uint32_t mem_word = Mem.uw;\n' 581 decl_code += 'uint32_t unalign_addr = Rs + disp;\n' 582 decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n' 583 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 584 decl_code += '\tbyte_offset ^= 3;\n' 585 decl_code += '#endif\n' 586 587 memacc_code = decl_code + memacc_code 588 589 (header_output, decoder_output, decode_block, exec_output) = \ 590 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 591 decode_template = ImmNopCheckDecode, 592 exec_template_base = 'Load') 593}}; 594 595def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 596 mem_flags = [], inst_flags = []) {{ 597 decl_code = 'uint32_t mem_word = 0;\n' 598 decl_code += 'uint32_t unaligned_addr = Rs + disp;\n' 599 decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n' 600 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 601 decl_code += '\tbyte_offset ^= 3;\n' 602 decl_code += '#endif\n' 603 decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n' 604 #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);' 605 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 606 607 (header_output, decoder_output, decode_block, exec_output) = \ 608 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 609 exec_template_base = 'Store') 610}}; 611 612def format Prefetch(ea_code = {{ EA = Rs + disp; }}, 613 mem_flags = [], pf_flags = [], inst_flags = []) {{ 614 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 615 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 616 'IsDataPrefetch', 'MemReadOp'] 617 618 (header_output, decoder_output, decode_block, exec_output) = \ 619 LoadStoreBase(name, Name, ea_code, 620 'xc->prefetch(EA, memAccessFlags);', 621 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 622 623}}; 624 625def format StoreCond(memacc_code, postacc_code, 626 ea_code = {{ EA = Rs + disp; }}, 627 mem_flags = [], inst_flags = []) {{ 628 (header_output, decoder_output, decode_block, exec_output) = \ 629 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 630 postacc_code, exec_template_base = 'StoreCond') 631}}; 632