mem.isa revision 6207:c47f3e877a57 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30//          Korey Sewell
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions
35//
36
37output header {{
38    /**
39     * Base class for general Mips memory-format instructions.
40     */
41    class Memory : public MipsStaticInst
42    {
43      protected:
44        /// Memory request flags.  See mem_req_base.hh.
45        Request::Flags memAccessFlags;
46
47        /// Displacement for EA calculation (signed).
48        int32_t disp;
49
50        /// Constructor
51        Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
52            : MipsStaticInst(mnem, _machInst, __opClass),
53              disp(sext<16>(OFFSET))
54        {
55        }
56
57        std::string
58        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
59    };
60
61     /**
62     * Base class for a few miscellaneous memory-format insts
63     * that don't interpret the disp field
64     */
65    class MemoryNoDisp : public Memory
66    {
67      protected:
68        /// Constructor
69        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70            : Memory(mnem, _machInst, __opClass)
71        {
72        }
73
74        std::string
75        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
76    };
77}};
78
79
80output decoder {{
81    std::string
82    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
83    {
84        return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
85                        flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
86    }
87
88    std::string
89    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
90    {
91        return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
92                        flags[IsFloating] ? 'f' : 'r',
93                        flags[IsFloating] ? FD : RD,
94                        RS, RT);
95    }
96
97}};
98
99output exec {{
100    /** return data in cases where there the size of data is only
101        known in the packet
102    */
103    uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) {
104        switch (packet->getSize())
105        {
106          case 1:
107            return packet->get<uint8_t>();
108
109          case 2:
110            return packet->get<uint16_t>();
111
112          case 4:
113            return packet->get<uint32_t>();
114
115          case 8:
116            return packet->get<uint64_t>();
117
118          default:
119            std::cerr << "bad store data size = " << packet->getSize() << std::endl;
120
121            assert(0);
122            return 0;
123        }
124    }
125
126
127}};
128
129def template LoadStoreDeclare {{
130    /**
131     * Static instruction class for "%(mnemonic)s".
132     */
133    class %(class_name)s : public %(base_class)s
134    {
135      public:
136
137        /// Constructor.
138        %(class_name)s(ExtMachInst machInst);
139
140        %(BasicExecDeclare)s
141
142        %(EACompDeclare)s
143
144        %(InitiateAccDeclare)s
145
146        %(CompleteAccDeclare)s
147    };
148}};
149
150def template EACompDeclare {{
151    Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
152}};
153
154def template InitiateAccDeclare {{
155    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
156}};
157
158
159def template CompleteAccDeclare {{
160    Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
161}};
162
163def template LoadStoreConstructor {{
164    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
165         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
166    {
167        %(constructor)s;
168    }
169}};
170
171
172def template EACompExecute {{
173    Fault
174    %(class_name)s::eaComp(%(CPU_exec_context)s *xc,
175                                   Trace::InstRecord *traceData) const
176    {
177        Addr EA;
178        Fault fault = NoFault;
179
180        if (this->isFloating()) {
181            %(fp_enable_check)s;
182
183            if(fault != NoFault)
184                return fault;
185        }
186
187        %(op_decl)s;
188        %(op_rd)s;
189        %(ea_code)s;
190
191        // NOTE: Trace Data is written using execute or completeAcc templates
192        if (fault == NoFault) {
193            xc->setEA(EA);
194        }
195
196        return fault;
197    }
198}};
199
200def template LoadExecute {{
201    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
202                                  Trace::InstRecord *traceData) const
203    {
204        Addr EA;
205        Fault fault = NoFault;
206
207        if (this->isFloating()) {
208            %(fp_enable_check)s;
209
210            if(fault != NoFault)
211                return fault;
212        }
213
214        %(op_decl)s;
215        %(op_rd)s;
216        %(ea_code)s;
217
218        if (fault == NoFault) {
219            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
220            %(memacc_code)s;
221        }
222
223        if (fault == NoFault) {
224            %(op_wb)s;
225        }
226
227        return fault;
228    }
229}};
230
231
232def template LoadInitiateAcc {{
233    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
234                                      Trace::InstRecord *traceData) const
235    {
236        Addr EA;
237        Fault fault = NoFault;
238
239        if (this->isFloating()) {
240            %(fp_enable_check)s;
241
242            if(fault != NoFault)
243                return fault;
244        }
245
246        %(op_src_decl)s;
247        %(op_rd)s;
248        %(ea_code)s;
249
250        if (fault == NoFault) {
251            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
252        }
253
254        return fault;
255    }
256}};
257
258def template LoadCompleteAcc {{
259    Fault %(class_name)s::completeAcc(Packet *pkt,
260                                      %(CPU_exec_context)s *xc,
261                                      Trace::InstRecord *traceData) const
262    {
263        Fault fault = NoFault;
264
265        if (this->isFloating()) {
266            %(fp_enable_check)s;
267
268            if(fault != NoFault)
269                return fault;
270        }
271
272        %(op_decl)s;
273        %(op_rd)s;
274
275        Mem = pkt->get<typeof(Mem)>();
276
277        if (fault == NoFault) {
278            %(memacc_code)s;
279        }
280
281        if (fault == NoFault) {
282            %(op_wb)s;
283        }
284
285        return fault;
286    }
287}};
288
289def template StoreExecute {{
290    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
291                                  Trace::InstRecord *traceData) const
292    {
293        Addr EA;
294        Fault fault = NoFault;
295
296        %(fp_enable_check)s;
297        %(op_decl)s;
298        %(op_rd)s;
299        %(ea_code)s;
300
301        if (fault == NoFault) {
302            %(memacc_code)s;
303        }
304
305        if (fault == NoFault) {
306            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
307                              memAccessFlags, NULL);
308            if (traceData) { traceData->setData(Mem); }
309        }
310
311        if (fault == NoFault) {
312            %(postacc_code)s;
313        }
314
315        if (fault == NoFault) {
316            %(op_wb)s;
317        }
318
319        return fault;
320    }
321}};
322
323
324def template StoreFPExecute {{
325    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
326                                  Trace::InstRecord *traceData) const
327    {
328        Addr EA;
329        Fault fault = NoFault;
330
331        %(fp_enable_check)s;
332        if(fault != NoFault)
333          return fault;
334        %(op_decl)s;
335        %(op_rd)s;
336        %(ea_code)s;
337
338        if (fault == NoFault) {
339            %(memacc_code)s;
340        }
341
342        if (fault == NoFault) {
343            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
344                              memAccessFlags, NULL);
345            if (traceData) { traceData->setData(Mem); }
346        }
347
348        if (fault == NoFault) {
349            %(postacc_code)s;
350        }
351
352        if (fault == NoFault) {
353            %(op_wb)s;
354        }
355
356        return fault;
357    }
358}};
359
360def template StoreCondExecute {{
361    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
362                                  Trace::InstRecord *traceData) const
363    {
364        Addr EA;
365        Fault fault = NoFault;
366        uint64_t write_result = 0;
367
368        %(fp_enable_check)s;
369        %(op_decl)s;
370        %(op_rd)s;
371        %(ea_code)s;
372
373        if (fault == NoFault) {
374            %(memacc_code)s;
375        }
376
377        if (fault == NoFault) {
378            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
379                              memAccessFlags, &write_result);
380            if (traceData) { traceData->setData(Mem); }
381        }
382
383        if (fault == NoFault) {
384            %(postacc_code)s;
385        }
386
387        if (fault == NoFault) {
388            %(op_wb)s;
389        }
390
391        return fault;
392    }
393}};
394
395def template StoreInitiateAcc {{
396    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
397                                      Trace::InstRecord *traceData) const
398    {
399        Addr EA;
400        Fault fault = NoFault;
401
402        %(fp_enable_check)s;
403        %(op_decl)s;
404        %(op_rd)s;
405        %(ea_code)s;
406
407        if (fault == NoFault) {
408            %(memacc_code)s;
409        }
410
411        if (fault == NoFault) {
412            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
413                              memAccessFlags, NULL);
414            if (traceData) { traceData->setData(Mem); }
415        }
416
417        return fault;
418    }
419}};
420
421
422def template StoreCompleteAcc {{
423    Fault %(class_name)s::completeAcc(Packet *pkt,
424                                      %(CPU_exec_context)s *xc,
425                                      Trace::InstRecord *traceData) const
426    {
427        Fault fault = NoFault;
428
429        %(fp_enable_check)s;
430        %(op_dest_decl)s;
431
432        if (fault == NoFault) {
433            %(postacc_code)s;
434        }
435
436        if (fault == NoFault) {
437            %(op_wb)s;
438
439            if (traceData) { traceData->setData(getMemData(xc, pkt)); }
440        }
441
442        return fault;
443    }
444}};
445
446
447def template StoreCompleteAcc {{
448    Fault %(class_name)s::completeAcc(Packet *pkt,
449                                      %(CPU_exec_context)s *xc,
450                                      Trace::InstRecord *traceData) const
451    {
452        Fault fault = NoFault;
453
454        %(op_dest_decl)s;
455
456        if (fault == NoFault) {
457            %(postacc_code)s;
458        }
459
460        if (fault == NoFault) {
461            %(op_wb)s;
462
463            if (traceData) { traceData->setData(getMemData(xc, pkt)); }
464        }
465
466        return fault;
467    }
468}};
469
470def template StoreCondCompleteAcc {{
471    Fault %(class_name)s::completeAcc(Packet *pkt,
472                                      %(CPU_exec_context)s *xc,
473                                      Trace::InstRecord *traceData) const
474    {
475        Fault fault = NoFault;
476
477        %(fp_enable_check)s;
478        %(op_dest_decl)s;
479
480        uint64_t write_result = pkt->req->getExtraData();
481
482        if (fault == NoFault) {
483            %(postacc_code)s;
484        }
485
486        if (fault == NoFault) {
487            %(op_wb)s;
488        }
489
490        return fault;
491    }
492}};
493
494def template MiscExecute {{
495    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
496                                  Trace::InstRecord *traceData) const
497    {
498        Addr EA;
499        Fault fault = NoFault;
500
501        %(fp_enable_check)s;
502        %(op_decl)s;
503        %(op_rd)s;
504        %(ea_code)s;
505
506        if (fault == NoFault) {
507            %(memacc_code)s;
508        }
509
510        return NoFault;
511    }
512}};
513
514def template MiscInitiateAcc {{
515    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
516                                      Trace::InstRecord *traceData) const
517    {
518        panic("Misc instruction does not support split access method!");
519        return NoFault;
520    }
521}};
522
523
524def template MiscCompleteAcc {{
525    Fault %(class_name)s::completeAcc(Packet *pkt,
526                                      %(CPU_exec_context)s *xc,
527                                      Trace::InstRecord *traceData) const
528    {
529        panic("Misc instruction does not support split access method!");
530
531        return NoFault;
532    }
533}};
534
535def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
536                     mem_flags = [], inst_flags = []) {{
537    (header_output, decoder_output, decode_block, exec_output) = \
538        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
539                      decode_template = ImmNopCheckDecode,
540                      exec_template_base = 'Load')
541}};
542
543
544def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
545                     mem_flags = [], inst_flags = []) {{
546    (header_output, decoder_output, decode_block, exec_output) = \
547        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
548                      exec_template_base = 'Store')
549}};
550
551def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
552                     mem_flags = [], inst_flags = []) {{
553    inst_flags += ['IsIndexed']
554    (header_output, decoder_output, decode_block, exec_output) = \
555        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
556                      decode_template = ImmNopCheckDecode,
557                      exec_template_base = 'Load')
558}};
559
560def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
561                     mem_flags = [], inst_flags = []) {{
562    inst_flags += ['IsIndexed']
563    (header_output, decoder_output, decode_block, exec_output) = \
564        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
565                      exec_template_base = 'Store')
566}};
567
568def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
569                     mem_flags = [], inst_flags = []) {{
570    inst_flags += ['IsIndexed', 'IsFloating']
571    (header_output, decoder_output, decode_block, exec_output) = \
572        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
573                      decode_template = ImmNopCheckDecode,
574                      exec_template_base = 'Load')
575}};
576
577def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
578                     mem_flags = [], inst_flags = []) {{
579    inst_flags += ['IsIndexed', 'IsFloating']
580    (header_output, decoder_output, decode_block, exec_output) = \
581        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
582                      exec_template_base = 'Store')
583}};
584
585
586def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
587                     mem_flags = [], inst_flags = []) {{
588    decl_code = 'uint32_t mem_word = Mem.uw;\n'
589    decl_code += 'uint32_t unalign_addr = Rs + disp;\n'
590    decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n'
591    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
592    decl_code += '\tbyte_offset ^= 3;\n'
593    decl_code += '#endif\n'
594
595    memacc_code = decl_code + memacc_code
596
597    (header_output, decoder_output, decode_block, exec_output) = \
598        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
599                      decode_template = ImmNopCheckDecode,
600                      exec_template_base = 'Load')
601}};
602
603def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
604                     mem_flags = [], inst_flags = []) {{
605    decl_code = 'uint32_t mem_word = 0;\n'
606    decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
607    decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
608    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
609    decl_code += '\tbyte_offset ^= 3;\n'
610    decl_code += '#endif\n'
611    decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
612    #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);'
613    memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
614
615    (header_output, decoder_output, decode_block, exec_output) = \
616        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
617                      exec_template_base = 'Store')
618}};
619
620def format Prefetch(ea_code = {{ EA = Rs + disp; }},
621                          mem_flags = [], pf_flags = [], inst_flags = []) {{
622    pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
623    pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
624                                  'IsDataPrefetch', 'MemReadOp']
625
626    (header_output, decoder_output, decode_block, exec_output) = \
627        LoadStoreBase(name, Name, ea_code,
628                      'xc->prefetch(EA, memAccessFlags);',
629                      pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
630
631}};
632
633def format StoreCond(memacc_code, postacc_code,
634                     ea_code = {{ EA = Rs + disp; }},
635                     mem_flags = [], inst_flags = []) {{
636    (header_output, decoder_output, decode_block, exec_output) = \
637        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
638                      postacc_code, exec_template_base = 'StoreCond')
639}};
640