mem.isa revision 3953:300d526414e6 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30//          Korey Sewell
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions
35//
36
37output header {{
38    /**
39     * Base class for general Mips memory-format instructions.
40     */
41    class Memory : public MipsStaticInst
42    {
43      protected:
44
45        /// Memory request flags.  See mem_req_base.hh.
46        unsigned memAccessFlags;
47        /// Pointer to EAComp object.
48        const StaticInstPtr eaCompPtr;
49        /// Pointer to MemAcc object.
50        const StaticInstPtr memAccPtr;
51
52        /// Displacement for EA calculation (signed).
53        int32_t disp;
54
55        /// Constructor
56        Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
57               StaticInstPtr _eaCompPtr = nullStaticInstPtr,
58               StaticInstPtr _memAccPtr = nullStaticInstPtr)
59            : MipsStaticInst(mnem, _machInst, __opClass),
60              memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
61              disp(sext<16>(OFFSET))
62        {
63        }
64
65        std::string
66        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
67
68      public:
69
70        const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
71        const StaticInstPtr &memAccInst() const { return memAccPtr; }
72    };
73
74     /**
75     * Base class for a few miscellaneous memory-format insts
76     * that don't interpret the disp field
77     */
78    class MemoryNoDisp : public Memory
79    {
80      protected:
81        /// Constructor
82        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
83                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
84                     StaticInstPtr _memAccPtr = nullStaticInstPtr)
85            : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
86        {
87        }
88
89        std::string
90        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
91    };
92}};
93
94
95output decoder {{
96    std::string
97    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
98    {
99        return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
100                        flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
101    }
102
103    std::string
104    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
105    {
106        return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
107                        flags[IsFloating] ? 'f' : 'r',
108                        flags[IsFloating] ? FD : RD,
109                        RS, RT);
110    }
111}};
112
113def template LoadStoreDeclare {{
114    /**
115     * Static instruction class for "%(mnemonic)s".
116     */
117    class %(class_name)s : public %(base_class)s
118    {
119      protected:
120
121        /**
122         * "Fake" effective address computation class for "%(mnemonic)s".
123         */
124        class EAComp : public %(base_class)s
125        {
126          public:
127            /// Constructor
128            EAComp(MachInst machInst);
129
130            %(BasicExecDeclare)s
131        };
132
133        /**
134         * "Fake" memory access instruction class for "%(mnemonic)s".
135         */
136        class MemAcc : public %(base_class)s
137        {
138          public:
139            /// Constructor
140            MemAcc(MachInst machInst);
141
142            %(BasicExecDeclare)s
143        };
144
145      public:
146
147        /// Constructor.
148        %(class_name)s(MachInst machInst);
149
150        %(BasicExecDeclare)s
151
152        %(InitiateAccDeclare)s
153
154        %(CompleteAccDeclare)s
155    };
156}};
157
158
159def template InitiateAccDeclare {{
160    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
161}};
162
163
164def template CompleteAccDeclare {{
165    Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
166}};
167
168
169def template EACompConstructor {{
170    /** TODO: change op_class to AddrGenOp or something (requires
171     * creating new member of OpClass enum in op_class.hh, updating
172     * config files, etc.). */
173    inline %(class_name)s::EAComp::EAComp(MachInst machInst)
174        : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
175    {
176        %(constructor)s;
177    }
178}};
179
180
181def template MemAccConstructor {{
182    inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
183        : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
184    {
185        %(constructor)s;
186    }
187}};
188
189
190def template LoadStoreConstructor {{
191    inline %(class_name)s::%(class_name)s(MachInst machInst)
192         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
193                          new EAComp(machInst), new MemAcc(machInst))
194    {
195        %(constructor)s;
196    }
197}};
198
199
200def template EACompExecute {{
201    Fault
202    %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
203                                   Trace::InstRecord *traceData) const
204    {
205        Addr EA;
206        Fault fault = NoFault;
207
208        %(fp_enable_check)s;
209        %(op_decl)s;
210        %(op_rd)s;
211        %(ea_code)s;
212
213        if (fault == NoFault) {
214            %(op_wb)s;
215            xc->setEA(EA);
216        }
217
218        return fault;
219    }
220}};
221
222def template LoadMemAccExecute {{
223    Fault
224    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
225                                   Trace::InstRecord *traceData) const
226    {
227        Addr EA;
228        Fault fault = NoFault;
229
230        %(fp_enable_check)s;
231        %(op_decl)s;
232        %(op_rd)s;
233        EA = xc->getEA();
234
235        if (fault == NoFault) {
236            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
237            %(memacc_code)s;
238        }
239
240        if (fault == NoFault) {
241            %(op_wb)s;
242        }
243
244        return fault;
245    }
246}};
247
248
249def template LoadExecute {{
250    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
251                                  Trace::InstRecord *traceData) const
252    {
253        Addr EA;
254        Fault fault = NoFault;
255
256        %(fp_enable_check)s;
257        %(op_decl)s;
258        %(op_rd)s;
259        %(ea_code)s;
260
261        if (fault == NoFault) {
262            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
263            %(memacc_code)s;
264        }
265
266        if (fault == NoFault) {
267            %(op_wb)s;
268        }
269
270        return fault;
271    }
272}};
273
274
275def template LoadInitiateAcc {{
276    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
277                                      Trace::InstRecord *traceData) const
278    {
279        Addr EA;
280        Fault fault = NoFault;
281
282        %(fp_enable_check)s;
283        %(op_src_decl)s;
284        %(op_rd)s;
285        %(ea_code)s;
286
287        if (fault == NoFault) {
288            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
289        }
290
291        return fault;
292    }
293}};
294
295
296def template LoadCompleteAcc {{
297    Fault %(class_name)s::completeAcc(PacketPtr pkt,
298                                      %(CPU_exec_context)s *xc,
299                                      Trace::InstRecord *traceData) const
300    {
301        Fault fault = NoFault;
302
303        %(fp_enable_check)s;
304        %(op_decl)s;
305
306        Mem = pkt->get<typeof(Mem)>();
307
308        if (fault == NoFault) {
309            %(memacc_code)s;
310        }
311
312        if (fault == NoFault) {
313            %(op_wb)s;
314        }
315
316        return fault;
317    }
318}};
319
320
321def template StoreMemAccExecute {{
322    Fault
323    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
324                                   Trace::InstRecord *traceData) const
325    {
326        Addr EA;
327        Fault fault = NoFault;
328        uint64_t write_result = 0;
329
330        %(fp_enable_check)s;
331        %(op_decl)s;
332        %(op_rd)s;
333        EA = xc->getEA();
334
335        if (fault == NoFault) {
336            %(memacc_code)s;
337        }
338
339        if (fault == NoFault) {
340            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
341                              memAccessFlags, &write_result);
342            if (traceData) { traceData->setData(Mem); }
343        }
344
345        if (fault == NoFault) {
346            %(postacc_code)s;
347        }
348
349        if (fault == NoFault) {
350            %(op_wb)s;
351        }
352
353        return fault;
354    }
355}};
356
357
358def template StoreExecute {{
359    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
360                                  Trace::InstRecord *traceData) const
361    {
362        Addr EA;
363        Fault fault = NoFault;
364        uint64_t write_result = 0;
365
366        %(fp_enable_check)s;
367        %(op_decl)s;
368        %(op_rd)s;
369        %(ea_code)s;
370
371        if (fault == NoFault) {
372            %(memacc_code)s;
373        }
374
375        if (fault == NoFault) {
376            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
377                              memAccessFlags, &write_result);
378            if (traceData) { traceData->setData(Mem); }
379        }
380
381        if (fault == NoFault) {
382            %(postacc_code)s;
383        }
384
385        if (fault == NoFault) {
386            %(op_wb)s;
387        }
388
389        return fault;
390    }
391}};
392
393def template StoreInitiateAcc {{
394    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
395                                      Trace::InstRecord *traceData) const
396    {
397        Addr EA;
398        Fault fault = NoFault;
399
400        %(fp_enable_check)s;
401        %(op_decl)s;
402        %(op_rd)s;
403        %(ea_code)s;
404
405        if (fault == NoFault) {
406            %(memacc_code)s;
407        }
408
409        if (fault == NoFault) {
410            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
411                              memAccessFlags, NULL);
412            if (traceData) { traceData->setData(Mem); }
413        }
414
415        return fault;
416    }
417}};
418
419
420def template StoreCompleteAcc {{
421    Fault %(class_name)s::completeAcc(PacketPtr pkt,
422                                      %(CPU_exec_context)s *xc,
423                                      Trace::InstRecord *traceData) const
424    {
425        Fault fault = NoFault;
426
427        %(fp_enable_check)s;
428        %(op_dest_decl)s;
429
430        if (fault == NoFault) {
431            %(postacc_code)s;
432        }
433
434        if (fault == NoFault) {
435            %(op_wb)s;
436        }
437
438        return fault;
439    }
440}};
441
442def template StoreCondCompleteAcc {{
443    Fault %(class_name)s::completeAcc(PacketPtr pkt,
444                                      %(CPU_exec_context)s *xc,
445                                      Trace::InstRecord *traceData) const
446    {
447        Fault fault = NoFault;
448
449        %(fp_enable_check)s;
450        %(op_dest_decl)s;
451
452        uint64_t write_result = pkt->req->getScResult();
453
454        if (fault == NoFault) {
455            %(postacc_code)s;
456        }
457
458        if (fault == NoFault) {
459            %(op_wb)s;
460        }
461
462        return fault;
463    }
464}};
465
466
467def template MiscMemAccExecute {{
468    Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
469                                          Trace::InstRecord *traceData) const
470    {
471        Addr EA;
472        Fault fault = NoFault;
473
474        %(fp_enable_check)s;
475        %(op_decl)s;
476        %(op_rd)s;
477        EA = xc->getEA();
478
479        if (fault == NoFault) {
480            %(memacc_code)s;
481        }
482
483        return NoFault;
484    }
485}};
486
487def template MiscExecute {{
488    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
489                                  Trace::InstRecord *traceData) const
490    {
491        Addr EA;
492        Fault fault = NoFault;
493
494        %(fp_enable_check)s;
495        %(op_decl)s;
496        %(op_rd)s;
497        %(ea_code)s;
498
499        if (fault == NoFault) {
500            %(memacc_code)s;
501        }
502
503        return NoFault;
504    }
505}};
506
507def template MiscInitiateAcc {{
508    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
509                                      Trace::InstRecord *traceData) const
510    {
511        panic("Misc instruction does not support split access method!");
512        return NoFault;
513    }
514}};
515
516
517def template MiscCompleteAcc {{
518    Fault %(class_name)s::completeAcc(PacketPtr pkt,
519                                      %(CPU_exec_context)s *xc,
520                                      Trace::InstRecord *traceData) const
521    {
522        panic("Misc instruction does not support split access method!");
523
524        return NoFault;
525    }
526}};
527
528def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
529                     mem_flags = [], inst_flags = []) {{
530    (header_output, decoder_output, decode_block, exec_output) = \
531        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
532                      decode_template = ImmNopCheckDecode,
533                      exec_template_base = 'Load')
534}};
535
536def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
537                     mem_flags = [], inst_flags = []) {{
538    (header_output, decoder_output, decode_block, exec_output) = \
539        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
540                      exec_template_base = 'Store')
541}};
542
543def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
544                     mem_flags = [], inst_flags = []) {{
545    (header_output, decoder_output, decode_block, exec_output) = \
546        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
547                      decode_template = ImmNopCheckDecode,
548                      exec_template_base = 'Load')
549}};
550
551def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
552                     mem_flags = [], inst_flags = []) {{
553    (header_output, decoder_output, decode_block, exec_output) = \
554        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
555                      exec_template_base = 'Store')
556}};
557
558def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
559                     mem_flags = [], inst_flags = []) {{
560    decl_code = 'uint32_t mem_word = Mem.uw;\n'
561    decl_code += 'uint32_t unalign_addr = Rs + disp;\n'
562    decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n'
563    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
564    decl_code += '\tbyte_offset ^= 3;\n'
565    decl_code += '#endif\n'
566
567    memacc_code = decl_code + memacc_code
568
569    (header_output, decoder_output, decode_block, exec_output) = \
570        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
571                      decode_template = ImmNopCheckDecode,
572                      exec_template_base = 'Load')
573}};
574
575def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
576                     mem_flags = [], inst_flags = []) {{
577    decl_code = 'uint32_t mem_word = 0;\n'
578    decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
579    decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
580    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
581    decl_code += '\tbyte_offset ^= 3;\n'
582    decl_code += '#endif\n'
583    decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
584    memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
585
586    (header_output, decoder_output, decode_block, exec_output) = \
587        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
588                      exec_template_base = 'Store')
589}};
590
591def format Prefetch(ea_code = {{ EA = Rs + disp; }},
592                          mem_flags = [], pf_flags = [], inst_flags = []) {{
593    pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
594    pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
595                                  'IsDataPrefetch', 'MemReadOp']
596
597    (header_output, decoder_output, decode_block, exec_output) = \
598        LoadStoreBase(name, Name, ea_code,
599                      'xc->prefetch(EA, memAccessFlags);',
600                      pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
601
602}};
603
604def format StoreCond(memacc_code, postacc_code,
605                     ea_code = {{ EA = Rs + disp; }},
606                     mem_flags = [], inst_flags = []) {{
607    (header_output, decoder_output, decode_block, exec_output) = \
608        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
609                      postacc_code, exec_template_base = 'StoreCond')
610}};
611