mem.isa revision 2495 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2003-2005 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
29output header {{
30    /**
31     * Base class for general Mips memory-format instructions.
32     */
33    class Memory : public MipsStaticInst
34    {
35      protected:
36
37        /// Memory request flags.  See mem_req_base.hh.
38        unsigned memAccessFlags;
39        /// Pointer to EAComp object.
40        const StaticInstPtr eaCompPtr;
41        /// Pointer to MemAcc object.
42        const StaticInstPtr memAccPtr;
43
44        /// Displacement for EA calculation (signed).
45        int32_t disp;
46
47        /// Constructor
48        Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
49               StaticInstPtr _eaCompPtr = nullStaticInstPtr,
50               StaticInstPtr _memAccPtr = nullStaticInstPtr)
51            : MipsStaticInst(mnem, _machInst, __opClass),
52              memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
53              disp(OFFSET)
54        {
55            //If Bit 15 is 1 then Sign Extend
56            int32_t temp = disp & 0x00008000;
57
58            if (temp > 0) {
59                disp |= 0xFFFF0000;
60            }
61        }
62
63        std::string
64        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
65
66      public:
67
68        const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
69        const StaticInstPtr &memAccInst() const { return memAccPtr; }
70    };
71
72}};
73
74
75output decoder {{
76    std::string
77    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
78    {
79        return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
80                        flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
81    }
82
83}};
84
85def format LoadAddress(code) {{
86    iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
87    header_output = BasicDeclare.subst(iop)
88    decoder_output = BasicConstructor.subst(iop)
89    decode_block = BasicDecode.subst(iop)
90    exec_output = BasicExecute.subst(iop)
91}};
92
93
94def template LoadStoreDeclare {{
95    /**
96     * Static instruction class for "%(mnemonic)s".
97     */
98    class %(class_name)s : public %(base_class)s
99    {
100      protected:
101
102        /**
103         * "Fake" effective address computation class for "%(mnemonic)s".
104         */
105        class EAComp : public %(base_class)s
106        {
107          public:
108            /// Constructor
109            EAComp(MachInst machInst);
110
111            %(BasicExecDeclare)s
112        };
113
114        /**
115         * "Fake" memory access instruction class for "%(mnemonic)s".
116         */
117        class MemAcc : public %(base_class)s
118        {
119          public:
120            /// Constructor
121            MemAcc(MachInst machInst);
122
123            %(BasicExecDeclare)s
124        };
125
126      public:
127
128        /// Constructor.
129        %(class_name)s(MachInst machInst);
130
131        %(BasicExecDeclare)s
132
133        %(InitiateAccDeclare)s
134
135        %(CompleteAccDeclare)s
136    };
137}};
138
139
140def template InitiateAccDeclare {{
141    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
142}};
143
144
145def template CompleteAccDeclare {{
146    Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
147}};
148
149
150def template LoadStoreConstructor {{
151    /** TODO: change op_class to AddrGenOp or something (requires
152     * creating new member of OpClass enum in op_class.hh, updating
153     * config files, etc.). */
154    inline %(class_name)s::EAComp::EAComp(MachInst machInst)
155        : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
156    {
157        %(ea_constructor)s;
158    }
159
160    inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
161        : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
162    {
163        %(memacc_constructor)s;
164    }
165
166    inline %(class_name)s::%(class_name)s(MachInst machInst)
167         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
168                          new EAComp(machInst), new MemAcc(machInst))
169    {
170        %(constructor)s;
171    }
172}};
173
174
175def template EACompExecute {{
176    Fault
177    %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
178                                   Trace::InstRecord *traceData) const
179    {
180        Addr EA;
181        Fault fault = NoFault;
182
183        %(fp_enable_check)s;
184        %(op_decl)s;
185        %(op_rd)s;
186        %(code)s;
187
188        if (fault == NoFault) {
189            %(op_wb)s;
190            xc->setEA(EA);
191        }
192
193        return fault;
194    }
195}};
196
197def template LoadMemAccExecute {{
198    Fault
199    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
200                                   Trace::InstRecord *traceData) const
201    {
202        Fault fault = NoFault;
203        //Fill in Code for Out-of-Order CPUs
204        return fault;
205    }
206}};
207
208
209def template LoadExecute {{
210    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
211                                  Trace::InstRecord *traceData) const
212    {
213        Addr EA;
214        Fault fault = NoFault;
215
216        %(fp_enable_check)s;
217        %(op_decl)s;
218        %(op_rd)s;
219        %(ea_code)s;
220
221        if (fault == NoFault) {
222            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
223            %(memacc_code)s;
224        }
225
226        if (fault == NoFault) {
227            %(op_wb)s;
228        }
229
230        return fault;
231    }
232}};
233
234
235def template LoadInitiateAcc {{
236    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
237                                      Trace::InstRecord *traceData) const
238    {
239        Fault fault = NoFault;
240        //Fill in Code for Out-of-Order CPUs
241        return fault;
242    }
243}};
244
245
246def template LoadCompleteAcc {{
247    Fault %(class_name)s::completeAcc(uint8_t *data,
248                                      %(CPU_exec_context)s *xc,
249                                      Trace::InstRecord *traceData) const
250    {
251        Fault fault = NoFault;
252        //Fill in Code for Out-of-Order CPUs
253        return fault;
254    }
255}};
256
257
258def template StoreMemAccExecute {{
259    Fault
260    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
261                                   Trace::InstRecord *traceData) const
262    {
263        Fault fault = NoFault;
264        //Fill in Code for Out-of-Order CPUs
265        return fault;
266    }
267}};
268
269
270def template StoreExecute {{
271    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
272                                  Trace::InstRecord *traceData) const
273    {
274        Addr EA;
275        Fault fault = NoFault;
276        uint64_t write_result = 0;
277
278        %(fp_enable_check)s;
279        %(op_decl)s;
280        %(op_rd)s;
281        %(ea_code)s;
282
283        if (fault == NoFault) {
284            %(memacc_code)s;
285        }
286
287        if (fault == NoFault) {
288            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
289                              memAccessFlags, &write_result);
290            if (traceData) { traceData->setData(Mem); }
291        }
292
293        if (fault == NoFault) {
294            %(postacc_code)s;
295        }
296
297        if (fault == NoFault) {
298            %(op_wb)s;
299        }
300
301        return fault;
302    }
303}};
304
305def template StoreInitiateAcc {{
306    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
307                                      Trace::InstRecord *traceData) const
308    {
309        Fault fault = NoFault;
310        //Fill in Code for Out-of-Order CPUs
311        return fault;
312    }
313}};
314
315
316def template StoreCompleteAcc {{
317    Fault %(class_name)s::completeAcc(uint8_t *data,
318                                      %(CPU_exec_context)s *xc,
319                                      Trace::InstRecord *traceData) const
320    {
321        Fault fault = NoFault;
322        //Fill in Code for Out-of-Order CPUs
323        return fault;
324    }
325}};
326
327// load instructions use Rt as dest, so check for
328// Rt == 31 to detect nops
329def template LoadNopCheckDecode {{
330 {
331     MipsStaticInst *i = new %(class_name)s(machInst);
332     if (RT == 0) {
333         i = makeNop(i);
334     }
335     return i;
336 }
337}};
338
339def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
340                     mem_flags = [], inst_flags = []) {{
341    (header_output, decoder_output, decode_block, exec_output) = \
342        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
343                      decode_template = LoadNopCheckDecode,
344                      exec_template_base = 'Load')
345}};
346
347
348def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
349                     mem_flags = [], inst_flags = []) {{
350    (header_output, decoder_output, decode_block, exec_output) = \
351        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
352                      exec_template_base = 'Store')
353}};
354
355def format UnalignedStore(memacc_code, postacc_code,
356                     ea_code = {{ EA = Rb + disp; }},
357                     mem_flags = [], inst_flags = []) {{
358    (header_output, decoder_output, decode_block, exec_output) = \
359        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
360                      postacc_code, exec_template_base = 'Store')
361}};
362
363//FP loads are offloaded to these formats for now ...
364def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }},
365                      mem_flags = [], inst_flags = []) {{
366    (header_output, decoder_output, decode_block, exec_output) = \
367        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
368                      decode_template = LoadNopCheckDecode,
369                      exec_template_base = 'Load')
370}};
371
372
373//FP stores are offloaded to these formats for now ...
374def format StoreMemory2(ea_code = {{ EA = Rs + disp; }},memacc_code = {{ }},
375                      mem_flags = [], inst_flags = []) {{
376    (header_output, decoder_output, decode_block, exec_output) = \
377        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
378                      decode_template = LoadNopCheckDecode,
379                      exec_template_base = 'Store')
380}};
381
382