mem.isa revision 12236:126ac9da6050 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30//          Korey Sewell
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions
35//
36
37output header {{
38    /**
39     * Base class for general Mips memory-format instructions.
40     */
41    class Memory : public MipsStaticInst
42    {
43      protected:
44        /// Memory request flags.  See mem_req_base.hh.
45        Request::Flags memAccessFlags;
46
47        /// Displacement for EA calculation (signed).
48        int32_t disp;
49
50        /// Constructor
51        Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
52            : MipsStaticInst(mnem, _machInst, __opClass),
53              disp(sext<16>(OFFSET))
54        {
55        }
56
57        std::string
58        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
59    };
60
61     /**
62     * Base class for a few miscellaneous memory-format insts
63     * that don't interpret the disp field
64     */
65    class MemoryNoDisp : public Memory
66    {
67      protected:
68        /// Constructor
69        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70            : Memory(mnem, _machInst, __opClass)
71        {
72        }
73
74        std::string
75        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
76    };
77}};
78
79
80output decoder {{
81    std::string
82    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
83    {
84        return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
85                        flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
86    }
87
88    std::string
89    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
90    {
91        return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
92                        flags[IsFloating] ? 'f' : 'r',
93                        flags[IsFloating] ? FD : RD,
94                        RS, RT);
95    }
96
97}};
98
99output header {{
100    uint64_t getMemData(ExecContext *xc, Packet *packet);
101
102}};
103
104output exec {{
105    /** return data in cases where there the size of data is only
106        known in the packet
107    */
108    uint64_t getMemData(ExecContext *xc, Packet *packet) {
109        switch (packet->getSize())
110        {
111          case 1:
112            return packet->get<uint8_t>();
113
114          case 2:
115            return packet->get<uint16_t>();
116
117          case 4:
118            return packet->get<uint32_t>();
119
120          case 8:
121            return packet->get<uint64_t>();
122
123          default:
124            std::cerr << "bad store data size = " << packet->getSize() << std::endl;
125
126            assert(0);
127            return 0;
128        }
129    }
130
131
132}};
133
134def template LoadStoreDeclare {{
135    /**
136     * Static instruction class for "%(mnemonic)s".
137     */
138    class %(class_name)s : public %(base_class)s
139    {
140      public:
141
142        /// Constructor.
143        %(class_name)s(ExtMachInst machInst);
144
145        Fault execute(ExecContext *, Trace::InstRecord *) const;
146        Fault eaComp(ExecContext *, Trace::InstRecord *) const;
147        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
148        Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const;
149    };
150}};
151
152
153def template LoadStoreConstructor {{
154    %(class_name)s::%(class_name)s(ExtMachInst machInst)
155         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
156    {
157        %(constructor)s;
158    }
159}};
160
161
162def template EACompExecute {{
163    Fault
164    %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const
165    {
166        Addr EA;
167        Fault fault = NoFault;
168
169        if (this->isFloating()) {
170            %(fp_enable_check)s;
171
172            if(fault != NoFault)
173                return fault;
174        }
175
176        %(op_decl)s;
177        %(op_rd)s;
178        %(ea_code)s;
179
180        // NOTE: Trace Data is written using execute or completeAcc templates
181        if (fault == NoFault) {
182            xc->setEA(EA);
183        }
184
185        return fault;
186    }
187}};
188
189def template LoadExecute {{
190    Fault %(class_name)s::execute(ExecContext *xc,
191                                  Trace::InstRecord *traceData) const
192    {
193        Addr EA;
194        Fault fault = NoFault;
195
196        if (this->isFloating()) {
197            %(fp_enable_check)s;
198
199            if(fault != NoFault)
200                return fault;
201        }
202
203        %(op_decl)s;
204        %(op_rd)s;
205        %(ea_code)s;
206
207        if (fault == NoFault) {
208            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
209            %(memacc_code)s;
210        }
211
212        if (fault == NoFault) {
213            %(op_wb)s;
214        }
215
216        return fault;
217    }
218}};
219
220
221def template LoadInitiateAcc {{
222    Fault %(class_name)s::initiateAcc(ExecContext *xc,
223                                      Trace::InstRecord *traceData) const
224    {
225        Addr EA;
226        Fault fault = NoFault;
227
228        if (this->isFloating()) {
229            %(fp_enable_check)s;
230
231            if(fault != NoFault)
232                return fault;
233        }
234
235        %(op_src_decl)s;
236        %(op_rd)s;
237        %(ea_code)s;
238
239        if (fault == NoFault) {
240            fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
241        }
242
243        return fault;
244    }
245}};
246
247def template LoadCompleteAcc {{
248    Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
249                                      Trace::InstRecord *traceData) const
250    {
251        Fault fault = NoFault;
252
253        if (this->isFloating()) {
254            %(fp_enable_check)s;
255
256            if(fault != NoFault)
257                return fault;
258        }
259
260        %(op_decl)s;
261        %(op_rd)s;
262
263        getMem(pkt, Mem, traceData);
264
265        if (fault == NoFault) {
266            %(memacc_code)s;
267        }
268
269        if (fault == NoFault) {
270            %(op_wb)s;
271        }
272
273        return fault;
274    }
275}};
276
277def template StoreExecute {{
278    Fault %(class_name)s::execute(ExecContext *xc,
279                                  Trace::InstRecord *traceData) const
280    {
281        Addr EA;
282        Fault fault = NoFault;
283
284        %(fp_enable_check)s;
285        %(op_decl)s;
286        %(op_rd)s;
287        %(ea_code)s;
288
289        if (fault == NoFault) {
290            %(memacc_code)s;
291        }
292
293        if (fault == NoFault) {
294            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
295                    NULL);
296        }
297
298        if (fault == NoFault) {
299            %(postacc_code)s;
300        }
301
302        if (fault == NoFault) {
303            %(op_wb)s;
304        }
305
306        return fault;
307    }
308}};
309
310
311def template StoreFPExecute {{
312    Fault %(class_name)s::execute(ExecContext *xc,
313                                  Trace::InstRecord *traceData) const
314    {
315        Addr EA;
316        Fault fault = NoFault;
317
318        %(fp_enable_check)s;
319        if(fault != NoFault)
320          return fault;
321        %(op_decl)s;
322        %(op_rd)s;
323        %(ea_code)s;
324
325        if (fault == NoFault) {
326            %(memacc_code)s;
327        }
328
329        if (fault == NoFault) {
330            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
331                    NULL);
332        }
333
334        if (fault == NoFault) {
335            %(postacc_code)s;
336        }
337
338        if (fault == NoFault) {
339            %(op_wb)s;
340        }
341
342        return fault;
343    }
344}};
345
346def template StoreCondExecute {{
347    Fault %(class_name)s::execute(ExecContext *xc,
348                                  Trace::InstRecord *traceData) const
349    {
350        Addr EA;
351        Fault fault = NoFault;
352        uint64_t write_result = 0;
353
354        %(fp_enable_check)s;
355        %(op_decl)s;
356        %(op_rd)s;
357        %(ea_code)s;
358
359        if (fault == NoFault) {
360            %(memacc_code)s;
361        }
362
363        if (fault == NoFault) {
364            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
365                    &write_result);
366        }
367
368        if (fault == NoFault) {
369            %(postacc_code)s;
370        }
371
372        if (fault == NoFault) {
373            %(op_wb)s;
374        }
375
376        return fault;
377    }
378}};
379
380def template StoreInitiateAcc {{
381    Fault %(class_name)s::initiateAcc(ExecContext *xc,
382                                      Trace::InstRecord *traceData) const
383    {
384        Addr EA;
385        Fault fault = NoFault;
386
387        %(fp_enable_check)s;
388        %(op_decl)s;
389        %(op_rd)s;
390        %(ea_code)s;
391
392        if (fault == NoFault) {
393            %(memacc_code)s;
394        }
395
396        if (fault == NoFault) {
397            fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
398                    NULL);
399        }
400
401        return fault;
402    }
403}};
404
405
406def template StoreCompleteAcc {{
407    Fault %(class_name)s::completeAcc(Packet *pkt,
408                                      ExecContext *xc,
409                                      Trace::InstRecord *traceData) const
410    {
411        return NoFault;
412    }
413}};
414
415def template StoreCondCompleteAcc {{
416    Fault %(class_name)s::completeAcc(Packet *pkt,
417                                      ExecContext *xc,
418                                      Trace::InstRecord *traceData) const
419    {
420        Fault fault = NoFault;
421
422        %(fp_enable_check)s;
423        %(op_dest_decl)s;
424
425        uint64_t write_result = pkt->req->getExtraData();
426
427        if (fault == NoFault) {
428            %(postacc_code)s;
429        }
430
431        if (fault == NoFault) {
432            %(op_wb)s;
433        }
434
435        return fault;
436    }
437}};
438
439def template MiscExecute {{
440    Fault %(class_name)s::execute(ExecContext *xc,
441                                  Trace::InstRecord *traceData) const
442    {
443        Addr EA M5_VAR_USED = 0;
444        Fault fault = NoFault;
445
446        %(fp_enable_check)s;
447        %(op_decl)s;
448        %(op_rd)s;
449        %(ea_code)s;
450
451        if (fault == NoFault) {
452            %(memacc_code)s;
453        }
454
455        return NoFault;
456    }
457}};
458
459def template MiscInitiateAcc {{
460    Fault %(class_name)s::initiateAcc(ExecContext *xc,
461                                      Trace::InstRecord *traceData) const
462    {
463        panic("Misc instruction does not support split access method!");
464        return NoFault;
465    }
466}};
467
468
469def template MiscCompleteAcc {{
470    Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
471                                      Trace::InstRecord *traceData) const
472    {
473        panic("Misc instruction does not support split access method!");
474
475        return NoFault;
476    }
477}};
478
479def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
480                     mem_flags = [], inst_flags = []) {{
481    (header_output, decoder_output, decode_block, exec_output) = \
482        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
483                      decode_template = ImmNopCheckDecode,
484                      exec_template_base = 'Load')
485}};
486
487
488def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
489                     mem_flags = [], inst_flags = []) {{
490    (header_output, decoder_output, decode_block, exec_output) = \
491        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
492                      exec_template_base = 'Store')
493}};
494
495def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
496                     mem_flags = [], inst_flags = []) {{
497    inst_flags += ['IsIndexed']
498    (header_output, decoder_output, decode_block, exec_output) = \
499        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
500                      decode_template = ImmNopCheckDecode,
501                      exec_template_base = 'Load')
502}};
503
504def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
505                     mem_flags = [], inst_flags = []) {{
506    inst_flags += ['IsIndexed']
507    (header_output, decoder_output, decode_block, exec_output) = \
508        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
509                      exec_template_base = 'Store')
510}};
511
512def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
513                     mem_flags = [], inst_flags = []) {{
514    inst_flags += ['IsIndexed', 'IsFloating']
515    (header_output, decoder_output, decode_block, exec_output) = \
516        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
517                      decode_template = ImmNopCheckDecode,
518                      exec_template_base = 'Load')
519}};
520
521def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
522                     mem_flags = [], inst_flags = []) {{
523    inst_flags += ['IsIndexed', 'IsFloating']
524    (header_output, decoder_output, decode_block, exec_output) = \
525        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
526                      exec_template_base = 'Store')
527}};
528
529
530def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
531                     mem_flags = [], inst_flags = []) {{
532    decl_code = '''
533        uint32_t mem_word = Mem_uw;
534        uint32_t unalign_addr = Rs + disp;
535        uint32_t byte_offset = unalign_addr & 3;
536        if (GuestByteOrder == BigEndianByteOrder)
537            byte_offset ^= 3;
538    '''
539
540    memacc_code = decl_code + memacc_code
541
542    (header_output, decoder_output, decode_block, exec_output) = \
543        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
544                      decode_template = ImmNopCheckDecode,
545                      exec_template_base = 'Load')
546}};
547
548def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
549                     mem_flags = [], inst_flags = []) {{
550    decl_code = '''
551        uint32_t mem_word = 0;
552        uint32_t unaligned_addr = Rs + disp;
553        uint32_t byte_offset = unaligned_addr & 3;
554        if (GuestByteOrder == BigEndianByteOrder)
555            byte_offset ^= 3;
556        fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
557    '''
558    memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
559
560    (header_output, decoder_output, decode_block, exec_output) = \
561        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
562                      exec_template_base = 'Store')
563}};
564
565def format Prefetch(ea_code = {{ EA = Rs + disp; }},
566                          mem_flags = [], pf_flags = [], inst_flags = []) {{
567    pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
568    pf_inst_flags = inst_flags
569
570    (header_output, decoder_output, decode_block, exec_output) = \
571        LoadStoreBase(name, Name, ea_code,
572                      'warn_once("Prefetching not implemented for MIPS\\n");',
573                      pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
574
575}};
576
577def format StoreCond(memacc_code, postacc_code,
578                     ea_code = {{ EA = Rs + disp; }},
579                     mem_flags = [], inst_flags = []) {{
580    (header_output, decoder_output, decode_block, exec_output) = \
581        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
582                      postacc_code, exec_template_base = 'StoreCond')
583}};
584