mem.isa revision 12234:78ece221f9f5 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30//          Korey Sewell
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions
35//
36
37output header {{
38    /**
39     * Base class for general Mips memory-format instructions.
40     */
41    class Memory : public MipsStaticInst
42    {
43      protected:
44        /// Memory request flags.  See mem_req_base.hh.
45        Request::Flags memAccessFlags;
46
47        /// Displacement for EA calculation (signed).
48        int32_t disp;
49
50        /// Constructor
51        Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
52            : MipsStaticInst(mnem, _machInst, __opClass),
53              disp(sext<16>(OFFSET))
54        {
55        }
56
57        std::string
58        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
59    };
60
61     /**
62     * Base class for a few miscellaneous memory-format insts
63     * that don't interpret the disp field
64     */
65    class MemoryNoDisp : public Memory
66    {
67      protected:
68        /// Constructor
69        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70            : Memory(mnem, _machInst, __opClass)
71        {
72        }
73
74        std::string
75        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
76    };
77}};
78
79
80output decoder {{
81    std::string
82    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
83    {
84        return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
85                        flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
86    }
87
88    std::string
89    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
90    {
91        return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
92                        flags[IsFloating] ? 'f' : 'r',
93                        flags[IsFloating] ? FD : RD,
94                        RS, RT);
95    }
96
97}};
98
99output header {{
100    uint64_t getMemData(ExecContext *xc, Packet *packet);
101
102}};
103
104output exec {{
105    /** return data in cases where there the size of data is only
106        known in the packet
107    */
108    uint64_t getMemData(ExecContext *xc, Packet *packet) {
109        switch (packet->getSize())
110        {
111          case 1:
112            return packet->get<uint8_t>();
113
114          case 2:
115            return packet->get<uint16_t>();
116
117          case 4:
118            return packet->get<uint32_t>();
119
120          case 8:
121            return packet->get<uint64_t>();
122
123          default:
124            std::cerr << "bad store data size = " << packet->getSize() << std::endl;
125
126            assert(0);
127            return 0;
128        }
129    }
130
131
132}};
133
134def template LoadStoreDeclare {{
135    /**
136     * Static instruction class for "%(mnemonic)s".
137     */
138    class %(class_name)s : public %(base_class)s
139    {
140      public:
141
142        /// Constructor.
143        %(class_name)s(ExtMachInst machInst);
144
145        %(BasicExecDeclare)s
146
147        %(EACompDeclare)s
148
149        %(InitiateAccDeclare)s
150
151        %(CompleteAccDeclare)s
152    };
153}};
154
155def template EACompDeclare {{
156    Fault eaComp(ExecContext *, Trace::InstRecord *) const;
157}};
158
159def template InitiateAccDeclare {{
160    Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
161}};
162
163
164def template CompleteAccDeclare {{
165    Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const;
166}};
167
168def template LoadStoreConstructor {{
169    %(class_name)s::%(class_name)s(ExtMachInst machInst)
170         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
171    {
172        %(constructor)s;
173    }
174}};
175
176
177def template EACompExecute {{
178    Fault
179    %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const
180    {
181        Addr EA;
182        Fault fault = NoFault;
183
184        if (this->isFloating()) {
185            %(fp_enable_check)s;
186
187            if(fault != NoFault)
188                return fault;
189        }
190
191        %(op_decl)s;
192        %(op_rd)s;
193        %(ea_code)s;
194
195        // NOTE: Trace Data is written using execute or completeAcc templates
196        if (fault == NoFault) {
197            xc->setEA(EA);
198        }
199
200        return fault;
201    }
202}};
203
204def template LoadExecute {{
205    Fault %(class_name)s::execute(ExecContext *xc,
206                                  Trace::InstRecord *traceData) const
207    {
208        Addr EA;
209        Fault fault = NoFault;
210
211        if (this->isFloating()) {
212            %(fp_enable_check)s;
213
214            if(fault != NoFault)
215                return fault;
216        }
217
218        %(op_decl)s;
219        %(op_rd)s;
220        %(ea_code)s;
221
222        if (fault == NoFault) {
223            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
224            %(memacc_code)s;
225        }
226
227        if (fault == NoFault) {
228            %(op_wb)s;
229        }
230
231        return fault;
232    }
233}};
234
235
236def template LoadInitiateAcc {{
237    Fault %(class_name)s::initiateAcc(ExecContext *xc,
238                                      Trace::InstRecord *traceData) const
239    {
240        Addr EA;
241        Fault fault = NoFault;
242
243        if (this->isFloating()) {
244            %(fp_enable_check)s;
245
246            if(fault != NoFault)
247                return fault;
248        }
249
250        %(op_src_decl)s;
251        %(op_rd)s;
252        %(ea_code)s;
253
254        if (fault == NoFault) {
255            fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
256        }
257
258        return fault;
259    }
260}};
261
262def template LoadCompleteAcc {{
263    Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
264                                      Trace::InstRecord *traceData) const
265    {
266        Fault fault = NoFault;
267
268        if (this->isFloating()) {
269            %(fp_enable_check)s;
270
271            if(fault != NoFault)
272                return fault;
273        }
274
275        %(op_decl)s;
276        %(op_rd)s;
277
278        getMem(pkt, Mem, traceData);
279
280        if (fault == NoFault) {
281            %(memacc_code)s;
282        }
283
284        if (fault == NoFault) {
285            %(op_wb)s;
286        }
287
288        return fault;
289    }
290}};
291
292def template StoreExecute {{
293    Fault %(class_name)s::execute(ExecContext *xc,
294                                  Trace::InstRecord *traceData) const
295    {
296        Addr EA;
297        Fault fault = NoFault;
298
299        %(fp_enable_check)s;
300        %(op_decl)s;
301        %(op_rd)s;
302        %(ea_code)s;
303
304        if (fault == NoFault) {
305            %(memacc_code)s;
306        }
307
308        if (fault == NoFault) {
309            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
310                    NULL);
311        }
312
313        if (fault == NoFault) {
314            %(postacc_code)s;
315        }
316
317        if (fault == NoFault) {
318            %(op_wb)s;
319        }
320
321        return fault;
322    }
323}};
324
325
326def template StoreFPExecute {{
327    Fault %(class_name)s::execute(ExecContext *xc,
328                                  Trace::InstRecord *traceData) const
329    {
330        Addr EA;
331        Fault fault = NoFault;
332
333        %(fp_enable_check)s;
334        if(fault != NoFault)
335          return fault;
336        %(op_decl)s;
337        %(op_rd)s;
338        %(ea_code)s;
339
340        if (fault == NoFault) {
341            %(memacc_code)s;
342        }
343
344        if (fault == NoFault) {
345            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
346                    NULL);
347        }
348
349        if (fault == NoFault) {
350            %(postacc_code)s;
351        }
352
353        if (fault == NoFault) {
354            %(op_wb)s;
355        }
356
357        return fault;
358    }
359}};
360
361def template StoreCondExecute {{
362    Fault %(class_name)s::execute(ExecContext *xc,
363                                  Trace::InstRecord *traceData) const
364    {
365        Addr EA;
366        Fault fault = NoFault;
367        uint64_t write_result = 0;
368
369        %(fp_enable_check)s;
370        %(op_decl)s;
371        %(op_rd)s;
372        %(ea_code)s;
373
374        if (fault == NoFault) {
375            %(memacc_code)s;
376        }
377
378        if (fault == NoFault) {
379            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
380                    &write_result);
381        }
382
383        if (fault == NoFault) {
384            %(postacc_code)s;
385        }
386
387        if (fault == NoFault) {
388            %(op_wb)s;
389        }
390
391        return fault;
392    }
393}};
394
395def template StoreInitiateAcc {{
396    Fault %(class_name)s::initiateAcc(ExecContext *xc,
397                                      Trace::InstRecord *traceData) const
398    {
399        Addr EA;
400        Fault fault = NoFault;
401
402        %(fp_enable_check)s;
403        %(op_decl)s;
404        %(op_rd)s;
405        %(ea_code)s;
406
407        if (fault == NoFault) {
408            %(memacc_code)s;
409        }
410
411        if (fault == NoFault) {
412            fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
413                    NULL);
414        }
415
416        return fault;
417    }
418}};
419
420
421def template StoreCompleteAcc {{
422    Fault %(class_name)s::completeAcc(Packet *pkt,
423                                      ExecContext *xc,
424                                      Trace::InstRecord *traceData) const
425    {
426        return NoFault;
427    }
428}};
429
430def template StoreCondCompleteAcc {{
431    Fault %(class_name)s::completeAcc(Packet *pkt,
432                                      ExecContext *xc,
433                                      Trace::InstRecord *traceData) const
434    {
435        Fault fault = NoFault;
436
437        %(fp_enable_check)s;
438        %(op_dest_decl)s;
439
440        uint64_t write_result = pkt->req->getExtraData();
441
442        if (fault == NoFault) {
443            %(postacc_code)s;
444        }
445
446        if (fault == NoFault) {
447            %(op_wb)s;
448        }
449
450        return fault;
451    }
452}};
453
454def template MiscExecute {{
455    Fault %(class_name)s::execute(ExecContext *xc,
456                                  Trace::InstRecord *traceData) const
457    {
458        Addr EA M5_VAR_USED = 0;
459        Fault fault = NoFault;
460
461        %(fp_enable_check)s;
462        %(op_decl)s;
463        %(op_rd)s;
464        %(ea_code)s;
465
466        if (fault == NoFault) {
467            %(memacc_code)s;
468        }
469
470        return NoFault;
471    }
472}};
473
474def template MiscInitiateAcc {{
475    Fault %(class_name)s::initiateAcc(ExecContext *xc,
476                                      Trace::InstRecord *traceData) const
477    {
478        panic("Misc instruction does not support split access method!");
479        return NoFault;
480    }
481}};
482
483
484def template MiscCompleteAcc {{
485    Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
486                                      Trace::InstRecord *traceData) const
487    {
488        panic("Misc instruction does not support split access method!");
489
490        return NoFault;
491    }
492}};
493
494def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
495                     mem_flags = [], inst_flags = []) {{
496    (header_output, decoder_output, decode_block, exec_output) = \
497        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
498                      decode_template = ImmNopCheckDecode,
499                      exec_template_base = 'Load')
500}};
501
502
503def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
504                     mem_flags = [], inst_flags = []) {{
505    (header_output, decoder_output, decode_block, exec_output) = \
506        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
507                      exec_template_base = 'Store')
508}};
509
510def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
511                     mem_flags = [], inst_flags = []) {{
512    inst_flags += ['IsIndexed']
513    (header_output, decoder_output, decode_block, exec_output) = \
514        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
515                      decode_template = ImmNopCheckDecode,
516                      exec_template_base = 'Load')
517}};
518
519def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
520                     mem_flags = [], inst_flags = []) {{
521    inst_flags += ['IsIndexed']
522    (header_output, decoder_output, decode_block, exec_output) = \
523        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
524                      exec_template_base = 'Store')
525}};
526
527def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
528                     mem_flags = [], inst_flags = []) {{
529    inst_flags += ['IsIndexed', 'IsFloating']
530    (header_output, decoder_output, decode_block, exec_output) = \
531        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
532                      decode_template = ImmNopCheckDecode,
533                      exec_template_base = 'Load')
534}};
535
536def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
537                     mem_flags = [], inst_flags = []) {{
538    inst_flags += ['IsIndexed', 'IsFloating']
539    (header_output, decoder_output, decode_block, exec_output) = \
540        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
541                      exec_template_base = 'Store')
542}};
543
544
545def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
546                     mem_flags = [], inst_flags = []) {{
547    decl_code = '''
548        uint32_t mem_word = Mem_uw;
549        uint32_t unalign_addr = Rs + disp;
550        uint32_t byte_offset = unalign_addr & 3;
551        if (GuestByteOrder == BigEndianByteOrder)
552            byte_offset ^= 3;
553    '''
554
555    memacc_code = decl_code + memacc_code
556
557    (header_output, decoder_output, decode_block, exec_output) = \
558        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
559                      decode_template = ImmNopCheckDecode,
560                      exec_template_base = 'Load')
561}};
562
563def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
564                     mem_flags = [], inst_flags = []) {{
565    decl_code = '''
566        uint32_t mem_word = 0;
567        uint32_t unaligned_addr = Rs + disp;
568        uint32_t byte_offset = unaligned_addr & 3;
569        if (GuestByteOrder == BigEndianByteOrder)
570            byte_offset ^= 3;
571        fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
572    '''
573    memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
574
575    (header_output, decoder_output, decode_block, exec_output) = \
576        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
577                      exec_template_base = 'Store')
578}};
579
580def format Prefetch(ea_code = {{ EA = Rs + disp; }},
581                          mem_flags = [], pf_flags = [], inst_flags = []) {{
582    pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
583    pf_inst_flags = inst_flags
584
585    (header_output, decoder_output, decode_block, exec_output) = \
586        LoadStoreBase(name, Name, ea_code,
587                      'warn_once("Prefetching not implemented for MIPS\\n");',
588                      pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
589
590}};
591
592def format StoreCond(memacc_code, postacc_code,
593                     ea_code = {{ EA = Rs + disp; }},
594                     mem_flags = [], inst_flags = []) {{
595    (header_output, decoder_output, decode_block, exec_output) = \
596        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
597                      postacc_code, exec_template_base = 'StoreCond')
598}};
599