mem.isa revision 8588
12124SN/A// -*- mode:c++ -*- 22124SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Steve Reinhardt 305268Sksewell@umich.edu// Korey Sewell 312022SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342706Sksewell@umich.edu// Memory-format instructions 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372022SN/Aoutput header {{ 382124SN/A /** 392124SN/A * Base class for general Mips memory-format instructions. 402124SN/A */ 412124SN/A class Memory : public MipsStaticInst 422124SN/A { 432124SN/A protected: 442124SN/A /// Memory request flags. See mem_req_base.hh. 455736Snate@binkert.org Request::Flags memAccessFlags; 462239SN/A 472124SN/A /// Displacement for EA calculation (signed). 482124SN/A int32_t disp; 492124SN/A 502124SN/A /// Constructor 516207Sksewell@umich.edu Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 522124SN/A : MipsStaticInst(mnem, _machInst, __opClass), 532742Sksewell@umich.edu disp(sext<16>(OFFSET)) 542022SN/A { 552124SN/A } 562022SN/A 572124SN/A std::string 582124SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 592124SN/A }; 602124SN/A 612742Sksewell@umich.edu /** 622742Sksewell@umich.edu * Base class for a few miscellaneous memory-format insts 632742Sksewell@umich.edu * that don't interpret the disp field 642742Sksewell@umich.edu */ 652742Sksewell@umich.edu class MemoryNoDisp : public Memory 662742Sksewell@umich.edu { 672742Sksewell@umich.edu protected: 682742Sksewell@umich.edu /// Constructor 696207Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 706207Sksewell@umich.edu : Memory(mnem, _machInst, __opClass) 712742Sksewell@umich.edu { 722742Sksewell@umich.edu } 732742Sksewell@umich.edu 742742Sksewell@umich.edu std::string 752742Sksewell@umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 762742Sksewell@umich.edu }; 772022SN/A}}; 782022SN/A 792124SN/A 802022SN/Aoutput decoder {{ 812124SN/A std::string 822124SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 832124SN/A { 842742Sksewell@umich.edu return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 852239SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 862124SN/A } 872124SN/A 882742Sksewell@umich.edu std::string 892742Sksewell@umich.edu MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 902742Sksewell@umich.edu { 912742Sksewell@umich.edu return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 922742Sksewell@umich.edu flags[IsFloating] ? 'f' : 'r', 932742Sksewell@umich.edu flags[IsFloating] ? FD : RD, 942742Sksewell@umich.edu RS, RT); 952742Sksewell@umich.edu } 964661Sksewell@umich.edu 974661Sksewell@umich.edu}}; 984661Sksewell@umich.edu 994661Sksewell@umich.eduoutput exec {{ 1004661Sksewell@umich.edu /** return data in cases where there the size of data is only 1014661Sksewell@umich.edu known in the packet 1024661Sksewell@umich.edu */ 1035222Sksewell@umich.edu uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) { 1044661Sksewell@umich.edu switch (packet->getSize()) 1054661Sksewell@umich.edu { 1065222Sksewell@umich.edu case 1: 1074661Sksewell@umich.edu return packet->get<uint8_t>(); 1084661Sksewell@umich.edu 1095222Sksewell@umich.edu case 2: 1104661Sksewell@umich.edu return packet->get<uint16_t>(); 1114661Sksewell@umich.edu 1125222Sksewell@umich.edu case 4: 1134661Sksewell@umich.edu return packet->get<uint32_t>(); 1144661Sksewell@umich.edu 1155222Sksewell@umich.edu case 8: 1164661Sksewell@umich.edu return packet->get<uint64_t>(); 1174661Sksewell@umich.edu 1184661Sksewell@umich.edu default: 1194661Sksewell@umich.edu std::cerr << "bad store data size = " << packet->getSize() << std::endl; 1204661Sksewell@umich.edu 1214661Sksewell@umich.edu assert(0); 1224661Sksewell@umich.edu return 0; 1234661Sksewell@umich.edu } 1244661Sksewell@umich.edu } 1254661Sksewell@umich.edu 1264661Sksewell@umich.edu 1272022SN/A}}; 1282022SN/A 1292124SN/Adef template LoadStoreDeclare {{ 1302124SN/A /** 1312124SN/A * Static instruction class for "%(mnemonic)s". 1322124SN/A */ 1332124SN/A class %(class_name)s : public %(base_class)s 1342124SN/A { 1352124SN/A public: 1362124SN/A 1372124SN/A /// Constructor. 1384661Sksewell@umich.edu %(class_name)s(ExtMachInst machInst); 1392124SN/A 1402124SN/A %(BasicExecDeclare)s 1412124SN/A 1426207Sksewell@umich.edu %(EACompDeclare)s 1436207Sksewell@umich.edu 1442124SN/A %(InitiateAccDeclare)s 1452124SN/A 1462124SN/A %(CompleteAccDeclare)s 1472124SN/A }; 1482022SN/A}}; 1492022SN/A 1506207Sksewell@umich.edudef template EACompDeclare {{ 1516207Sksewell@umich.edu Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1526207Sksewell@umich.edu}}; 1532124SN/A 1542124SN/Adef template InitiateAccDeclare {{ 1552132SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1562022SN/A}}; 1572124SN/A 1582124SN/A 1592124SN/Adef template CompleteAccDeclare {{ 1604661Sksewell@umich.edu Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1612124SN/A}}; 1622124SN/A 1636207Sksewell@umich.edudef template LoadStoreConstructor {{ 1646207Sksewell@umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1656207Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1662124SN/A { 1673953Sstever@eecs.umich.edu %(constructor)s; 1682124SN/A } 1693953Sstever@eecs.umich.edu}}; 1702124SN/A 1713953Sstever@eecs.umich.edu 1722124SN/Adef template EACompExecute {{ 1732132SN/A Fault 1746207Sksewell@umich.edu %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 1752124SN/A Trace::InstRecord *traceData) const 1762124SN/A { 1772124SN/A Addr EA; 1782132SN/A Fault fault = NoFault; 1792124SN/A 1805222Sksewell@umich.edu if (this->isFloating()) { 1815222Sksewell@umich.edu %(fp_enable_check)s; 1825222Sksewell@umich.edu 1835222Sksewell@umich.edu if(fault != NoFault) 1845222Sksewell@umich.edu return fault; 1855222Sksewell@umich.edu } 1865222Sksewell@umich.edu 1872124SN/A %(op_decl)s; 1882124SN/A %(op_rd)s; 1893953Sstever@eecs.umich.edu %(ea_code)s; 1902124SN/A 1914661Sksewell@umich.edu // NOTE: Trace Data is written using execute or completeAcc templates 1922124SN/A if (fault == NoFault) { 1932124SN/A xc->setEA(EA); 1942124SN/A } 1952124SN/A 1962124SN/A return fault; 1972124SN/A } 1982124SN/A}}; 1992124SN/A 2002124SN/Adef template LoadExecute {{ 2012132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2022124SN/A Trace::InstRecord *traceData) const 2032124SN/A { 2042124SN/A Addr EA; 2052132SN/A Fault fault = NoFault; 2062124SN/A 2075222Sksewell@umich.edu if (this->isFloating()) { 2085222Sksewell@umich.edu %(fp_enable_check)s; 2095222Sksewell@umich.edu 2105222Sksewell@umich.edu if(fault != NoFault) 2115222Sksewell@umich.edu return fault; 2125222Sksewell@umich.edu } 2135222Sksewell@umich.edu 2142124SN/A %(op_decl)s; 2152124SN/A %(op_rd)s; 2162124SN/A %(ea_code)s; 2172124SN/A 2182124SN/A if (fault == NoFault) { 2198442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 2202124SN/A %(memacc_code)s; 2212124SN/A } 2222124SN/A 2232124SN/A if (fault == NoFault) { 2242124SN/A %(op_wb)s; 2252124SN/A } 2262124SN/A 2272124SN/A return fault; 2282124SN/A } 2292124SN/A}}; 2302124SN/A 2312124SN/A 2322124SN/Adef template LoadInitiateAcc {{ 2332132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2342124SN/A Trace::InstRecord *traceData) const 2352124SN/A { 2362239SN/A Addr EA; 2372132SN/A Fault fault = NoFault; 2382239SN/A 2395222Sksewell@umich.edu if (this->isFloating()) { 2405222Sksewell@umich.edu %(fp_enable_check)s; 2415222Sksewell@umich.edu 2425222Sksewell@umich.edu if(fault != NoFault) 2435222Sksewell@umich.edu return fault; 2445222Sksewell@umich.edu } 2455222Sksewell@umich.edu 2462239SN/A %(op_src_decl)s; 2472239SN/A %(op_rd)s; 2482239SN/A %(ea_code)s; 2492239SN/A 2502239SN/A if (fault == NoFault) { 2518442Sgblack@eecs.umich.edu fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags); 2522239SN/A } 2532239SN/A 2542124SN/A return fault; 2552124SN/A } 2562124SN/A}}; 2572124SN/A 2582124SN/Adef template LoadCompleteAcc {{ 2594661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 2602124SN/A %(CPU_exec_context)s *xc, 2612124SN/A Trace::InstRecord *traceData) const 2622124SN/A { 2632132SN/A Fault fault = NoFault; 2642239SN/A 2655222Sksewell@umich.edu if (this->isFloating()) { 2665222Sksewell@umich.edu %(fp_enable_check)s; 2675222Sksewell@umich.edu 2685222Sksewell@umich.edu if(fault != NoFault) 2695222Sksewell@umich.edu return fault; 2705222Sksewell@umich.edu } 2715222Sksewell@umich.edu 2722506SN/A %(op_decl)s; 2734661Sksewell@umich.edu %(op_rd)s; 2742239SN/A 2758442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 2762239SN/A 2772239SN/A if (fault == NoFault) { 2782239SN/A %(memacc_code)s; 2792239SN/A } 2802239SN/A 2812239SN/A if (fault == NoFault) { 2822239SN/A %(op_wb)s; 2832239SN/A } 2842239SN/A 2852124SN/A return fault; 2862124SN/A } 2872124SN/A}}; 2882124SN/A 2892124SN/Adef template StoreExecute {{ 2902132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2912124SN/A Trace::InstRecord *traceData) const 2922124SN/A { 2932124SN/A Addr EA; 2942132SN/A Fault fault = NoFault; 2954056Sstever@eecs.umich.edu 2964056Sstever@eecs.umich.edu %(fp_enable_check)s; 2974056Sstever@eecs.umich.edu %(op_decl)s; 2984056Sstever@eecs.umich.edu %(op_rd)s; 2994056Sstever@eecs.umich.edu %(ea_code)s; 3004056Sstever@eecs.umich.edu 3014056Sstever@eecs.umich.edu if (fault == NoFault) { 3024056Sstever@eecs.umich.edu %(memacc_code)s; 3034056Sstever@eecs.umich.edu } 3044056Sstever@eecs.umich.edu 3054056Sstever@eecs.umich.edu if (fault == NoFault) { 3068442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3078442Sgblack@eecs.umich.edu NULL); 3084056Sstever@eecs.umich.edu } 3094056Sstever@eecs.umich.edu 3104056Sstever@eecs.umich.edu if (fault == NoFault) { 3114056Sstever@eecs.umich.edu %(postacc_code)s; 3124056Sstever@eecs.umich.edu } 3134056Sstever@eecs.umich.edu 3144056Sstever@eecs.umich.edu if (fault == NoFault) { 3154056Sstever@eecs.umich.edu %(op_wb)s; 3164056Sstever@eecs.umich.edu } 3174056Sstever@eecs.umich.edu 3184056Sstever@eecs.umich.edu return fault; 3194056Sstever@eecs.umich.edu } 3204056Sstever@eecs.umich.edu}}; 3214056Sstever@eecs.umich.edu 3225222Sksewell@umich.edu 3235222Sksewell@umich.edudef template StoreFPExecute {{ 3245222Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3255222Sksewell@umich.edu Trace::InstRecord *traceData) const 3265222Sksewell@umich.edu { 3275222Sksewell@umich.edu Addr EA; 3285222Sksewell@umich.edu Fault fault = NoFault; 3295222Sksewell@umich.edu 3305222Sksewell@umich.edu %(fp_enable_check)s; 3315222Sksewell@umich.edu if(fault != NoFault) 3325222Sksewell@umich.edu return fault; 3335222Sksewell@umich.edu %(op_decl)s; 3345222Sksewell@umich.edu %(op_rd)s; 3355222Sksewell@umich.edu %(ea_code)s; 3365222Sksewell@umich.edu 3375222Sksewell@umich.edu if (fault == NoFault) { 3385222Sksewell@umich.edu %(memacc_code)s; 3395222Sksewell@umich.edu } 3405222Sksewell@umich.edu 3415222Sksewell@umich.edu if (fault == NoFault) { 3428442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3438442Sgblack@eecs.umich.edu NULL); 3445222Sksewell@umich.edu } 3455222Sksewell@umich.edu 3465222Sksewell@umich.edu if (fault == NoFault) { 3475222Sksewell@umich.edu %(postacc_code)s; 3485222Sksewell@umich.edu } 3495222Sksewell@umich.edu 3505222Sksewell@umich.edu if (fault == NoFault) { 3515222Sksewell@umich.edu %(op_wb)s; 3525222Sksewell@umich.edu } 3535222Sksewell@umich.edu 3545222Sksewell@umich.edu return fault; 3555222Sksewell@umich.edu } 3565222Sksewell@umich.edu}}; 3575222Sksewell@umich.edu 3584056Sstever@eecs.umich.edudef template StoreCondExecute {{ 3594056Sstever@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3604056Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 3614056Sstever@eecs.umich.edu { 3624056Sstever@eecs.umich.edu Addr EA; 3634056Sstever@eecs.umich.edu Fault fault = NoFault; 3642124SN/A uint64_t write_result = 0; 3652124SN/A 3662124SN/A %(fp_enable_check)s; 3672124SN/A %(op_decl)s; 3682124SN/A %(op_rd)s; 3692124SN/A %(ea_code)s; 3702124SN/A 3712124SN/A if (fault == NoFault) { 3722124SN/A %(memacc_code)s; 3732124SN/A } 3742124SN/A 3752124SN/A if (fault == NoFault) { 3768442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3778442Sgblack@eecs.umich.edu &write_result); 3782124SN/A } 3792124SN/A 3802124SN/A if (fault == NoFault) { 3812124SN/A %(postacc_code)s; 3822124SN/A } 3832124SN/A 3842124SN/A if (fault == NoFault) { 3852124SN/A %(op_wb)s; 3862124SN/A } 3872124SN/A 3882124SN/A return fault; 3892124SN/A } 3902124SN/A}}; 3912124SN/A 3922124SN/Adef template StoreInitiateAcc {{ 3932132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3942124SN/A Trace::InstRecord *traceData) const 3952124SN/A { 3962239SN/A Addr EA; 3972132SN/A Fault fault = NoFault; 3982239SN/A 3992239SN/A %(fp_enable_check)s; 4002506SN/A %(op_decl)s; 4012239SN/A %(op_rd)s; 4022239SN/A %(ea_code)s; 4032239SN/A 4042239SN/A if (fault == NoFault) { 4052239SN/A %(memacc_code)s; 4062239SN/A } 4072239SN/A 4082239SN/A if (fault == NoFault) { 4098442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 4108442Sgblack@eecs.umich.edu NULL); 4112239SN/A } 4122239SN/A 4132124SN/A return fault; 4142124SN/A } 4152124SN/A}}; 4162124SN/A 4172124SN/A 4182124SN/Adef template StoreCompleteAcc {{ 4194661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 4202124SN/A %(CPU_exec_context)s *xc, 4212124SN/A Trace::InstRecord *traceData) const 4222124SN/A { 4237712Sgblack@eecs.umich.edu return NoFault; 4242935Sksewell@umich.edu } 4252935Sksewell@umich.edu}}; 4262935Sksewell@umich.edu 4272935Sksewell@umich.edudef template StoreCondCompleteAcc {{ 4284661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 4292935Sksewell@umich.edu %(CPU_exec_context)s *xc, 4302935Sksewell@umich.edu Trace::InstRecord *traceData) const 4312935Sksewell@umich.edu { 4322935Sksewell@umich.edu Fault fault = NoFault; 4332935Sksewell@umich.edu 4342935Sksewell@umich.edu %(fp_enable_check)s; 4352935Sksewell@umich.edu %(op_dest_decl)s; 4362935Sksewell@umich.edu 4374055Ssaidi@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 4382239SN/A 4392239SN/A if (fault == NoFault) { 4402239SN/A %(postacc_code)s; 4412239SN/A } 4422239SN/A 4432239SN/A if (fault == NoFault) { 4442239SN/A %(op_wb)s; 4452239SN/A } 4462239SN/A 4472124SN/A return fault; 4482124SN/A } 4492124SN/A}}; 4502124SN/A 4512686Sksewell@umich.edudef template MiscExecute {{ 4522686Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 4532686Sksewell@umich.edu Trace::InstRecord *traceData) const 4542686Sksewell@umich.edu { 4557725SAli.Saidi@ARM.com Addr EA M5_VAR_USED = 0; 4562686Sksewell@umich.edu Fault fault = NoFault; 4572686Sksewell@umich.edu 4582686Sksewell@umich.edu %(fp_enable_check)s; 4592686Sksewell@umich.edu %(op_decl)s; 4602686Sksewell@umich.edu %(op_rd)s; 4612686Sksewell@umich.edu %(ea_code)s; 4622686Sksewell@umich.edu 4632686Sksewell@umich.edu if (fault == NoFault) { 4642686Sksewell@umich.edu %(memacc_code)s; 4652686Sksewell@umich.edu } 4662686Sksewell@umich.edu 4672686Sksewell@umich.edu return NoFault; 4682686Sksewell@umich.edu } 4692686Sksewell@umich.edu}}; 4702686Sksewell@umich.edu 4712686Sksewell@umich.edudef template MiscInitiateAcc {{ 4722686Sksewell@umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4732686Sksewell@umich.edu Trace::InstRecord *traceData) const 4742686Sksewell@umich.edu { 4752686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4762686Sksewell@umich.edu return NoFault; 4772686Sksewell@umich.edu } 4782686Sksewell@umich.edu}}; 4792686Sksewell@umich.edu 4802686Sksewell@umich.edu 4812686Sksewell@umich.edudef template MiscCompleteAcc {{ 4824661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 4832686Sksewell@umich.edu %(CPU_exec_context)s *xc, 4842686Sksewell@umich.edu Trace::InstRecord *traceData) const 4852686Sksewell@umich.edu { 4862686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4872686Sksewell@umich.edu 4882686Sksewell@umich.edu return NoFault; 4892686Sksewell@umich.edu } 4902686Sksewell@umich.edu}}; 4912686Sksewell@umich.edu 4922124SN/Adef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4932124SN/A mem_flags = [], inst_flags = []) {{ 4942124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4952124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4962750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 4972124SN/A exec_template_base = 'Load') 4982124SN/A}}; 4992124SN/A 5005222Sksewell@umich.edu 5012124SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 5022124SN/A mem_flags = [], inst_flags = []) {{ 5032124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5042124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5052124SN/A exec_template_base = 'Store') 5062124SN/A}}; 5072124SN/A 5082686Sksewell@umich.edudef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5092573SN/A mem_flags = [], inst_flags = []) {{ 5105222Sksewell@umich.edu inst_flags += ['IsIndexed'] 5112573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5122573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5132750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5142573SN/A exec_template_base = 'Load') 5152573SN/A}}; 5162573SN/A 5172686Sksewell@umich.edudef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5182573SN/A mem_flags = [], inst_flags = []) {{ 5195222Sksewell@umich.edu inst_flags += ['IsIndexed'] 5202573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5212573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5222573SN/A exec_template_base = 'Store') 5232573SN/A}}; 5242573SN/A 5255222Sksewell@umich.edudef format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5265222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5275222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 5285222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5295222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5305222Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5315222Sksewell@umich.edu exec_template_base = 'Load') 5325222Sksewell@umich.edu}}; 5335222Sksewell@umich.edu 5345222Sksewell@umich.edudef format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5355222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5365222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 5375222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5385222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5395222Sksewell@umich.edu exec_template_base = 'Store') 5405222Sksewell@umich.edu}}; 5415222Sksewell@umich.edu 5425222Sksewell@umich.edu 5432686Sksewell@umich.edudef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5442686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5458564Sgblack@eecs.umich.edu decl_code = ''' 5468588Sgblack@eecs.umich.edu uint32_t mem_word = Mem_uw; 5478564Sgblack@eecs.umich.edu uint32_t unalign_addr = Rs + disp; 5488564Sgblack@eecs.umich.edu uint32_t byte_offset = unalign_addr & 3; 5498564Sgblack@eecs.umich.edu if (GuestByteOrder == BigEndianByteOrder) 5508564Sgblack@eecs.umich.edu byte_offset ^= 3; 5518564Sgblack@eecs.umich.edu ''' 5522573SN/A 5532686Sksewell@umich.edu memacc_code = decl_code + memacc_code 5542686Sksewell@umich.edu 5552686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5562686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5572750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5582686Sksewell@umich.edu exec_template_base = 'Load') 5592686Sksewell@umich.edu}}; 5602686Sksewell@umich.edu 5612686Sksewell@umich.edudef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5622686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5638442Sgblack@eecs.umich.edu decl_code = ''' 5648442Sgblack@eecs.umich.edu uint32_t mem_word = 0; 5658442Sgblack@eecs.umich.edu uint32_t unaligned_addr = Rs + disp; 5668442Sgblack@eecs.umich.edu uint32_t byte_offset = unaligned_addr & 3; 5678564Sgblack@eecs.umich.edu if (GuestByteOrder == BigEndianByteOrder) 5688442Sgblack@eecs.umich.edu byte_offset ^= 3; 5698442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags); 5708442Sgblack@eecs.umich.edu ''' 5712686Sksewell@umich.edu memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 5722686Sksewell@umich.edu 5732686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5742686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5752686Sksewell@umich.edu exec_template_base = 'Store') 5762686Sksewell@umich.edu}}; 5772686Sksewell@umich.edu 5782686Sksewell@umich.edudef format Prefetch(ea_code = {{ EA = Rs + disp; }}, 5792686Sksewell@umich.edu mem_flags = [], pf_flags = [], inst_flags = []) {{ 5806739Sgblack@eecs.umich.edu pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 5817725SAli.Saidi@ARM.com pf_inst_flags = inst_flags 5822686Sksewell@umich.edu 5832686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5842686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, 5857725SAli.Saidi@ARM.com 'warn_once("Prefetching not implemented for MIPS\\n");', 5862686Sksewell@umich.edu pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5872686Sksewell@umich.edu 5882686Sksewell@umich.edu}}; 5892686Sksewell@umich.edu 5902686Sksewell@umich.edudef format StoreCond(memacc_code, postacc_code, 5912686Sksewell@umich.edu ea_code = {{ EA = Rs + disp; }}, 5922495SN/A mem_flags = [], inst_flags = []) {{ 5932495SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5942495SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5952935Sksewell@umich.edu postacc_code, exec_template_base = 'StoreCond') 5962495SN/A}}; 597