mem.isa revision 7712
12440SN/A// -*- mode:c++ -*- 22440SN/A 32440SN/A// Copyright (c) 2007 MIPS Technologies, Inc. 42440SN/A// All rights reserved. 52440SN/A// 62440SN/A// Redistribution and use in source and binary forms, with or without 72440SN/A// modification, are permitted provided that the following conditions are 82440SN/A// met: redistributions of source code must retain the above copyright 92440SN/A// notice, this list of conditions and the following disclaimer; 102440SN/A// redistributions in binary form must reproduce the above copyright 112440SN/A// notice, this list of conditions and the following disclaimer in the 122440SN/A// documentation and/or other materials provided with the distribution; 132440SN/A// neither the name of the copyright holders nor the names of its 142440SN/A// contributors may be used to endorse or promote products derived from 152440SN/A// this software without specific prior written permission. 162440SN/A// 172440SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182440SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192440SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202440SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212440SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222440SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232440SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242440SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252440SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262440SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Steve Reinhardt 302440SN/A// Korey Sewell 312440SN/A 322440SN/A//////////////////////////////////////////////////////////////////// 332440SN/A// 342440SN/A// Memory-format instructions 352440SN/A// 362972Sgblack@eecs.umich.edu 376330Sgblack@eecs.umich.eduoutput header {{ 382440SN/A /** 395569Snate@binkert.org * Base class for general Mips memory-format instructions. 407720Sgblack@eecs.umich.edu */ 413120Sgblack@eecs.umich.edu class Memory : public MipsStaticInst 422440SN/A { 435569Snate@binkert.org protected: 445569Snate@binkert.org /// Memory request flags. See mem_req_base.hh. 457720Sgblack@eecs.umich.edu Request::Flags memAccessFlags; 467720Sgblack@eecs.umich.edu 477720Sgblack@eecs.umich.edu /// Displacement for EA calculation (signed). 487720Sgblack@eecs.umich.edu int32_t disp; 497720Sgblack@eecs.umich.edu 507720Sgblack@eecs.umich.edu /// Constructor 517720Sgblack@eecs.umich.edu Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 527720Sgblack@eecs.umich.edu : MipsStaticInst(mnem, _machInst, __opClass), 537707Sgblack@eecs.umich.edu disp(sext<16>(OFFSET)) 545569Snate@binkert.org { 555569Snate@binkert.org } 565569Snate@binkert.org 572440SN/A std::string 585569Snate@binkert.org generateDisassembly(Addr pc, const SymbolTable *symtab) const; 595569Snate@binkert.org }; 604826Ssaidi@eecs.umich.edu 615569Snate@binkert.org /** 625569Snate@binkert.org * Base class for a few miscellaneous memory-format insts 635569Snate@binkert.org * that don't interpret the disp field 645569Snate@binkert.org */ 655569Snate@binkert.org class MemoryNoDisp : public Memory 665569Snate@binkert.org { 672440SN/A protected: 685569Snate@binkert.org /// Constructor 695569Snate@binkert.org MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 705569Snate@binkert.org : Memory(mnem, _machInst, __opClass) 712440SN/A { 725569Snate@binkert.org } 735569Snate@binkert.org 745569Snate@binkert.org std::string 755569Snate@binkert.org generateDisassembly(Addr pc, const SymbolTable *symtab) const; 762440SN/A }; 775569Snate@binkert.org}}; 782440SN/A 795569Snate@binkert.org 805569Snate@binkert.orgoutput decoder {{ 812440SN/A std::string 825569Snate@binkert.org Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 835569Snate@binkert.org { 845569Snate@binkert.org return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 852440SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 865569Snate@binkert.org } 875569Snate@binkert.org 882440SN/A std::string 895569Snate@binkert.org MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 905569Snate@binkert.org { 915569Snate@binkert.org return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 922440SN/A flags[IsFloating] ? 'f' : 'r', 935569Snate@binkert.org flags[IsFloating] ? FD : RD, 945569Snate@binkert.org RS, RT); 955569Snate@binkert.org } 962440SN/A 975569Snate@binkert.org}}; 985569Snate@binkert.org 995569Snate@binkert.orgoutput exec {{ 1002440SN/A /** return data in cases where there the size of data is only 1012440SN/A known in the packet 1026329Sgblack@eecs.umich.edu */ 1036329Sgblack@eecs.umich.edu uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) { 1046329Sgblack@eecs.umich.edu switch (packet->getSize()) 1056329Sgblack@eecs.umich.edu { 1067693SAli.Saidi@ARM.com case 1: 1077720Sgblack@eecs.umich.edu return packet->get<uint8_t>(); 1087720Sgblack@eecs.umich.edu 1097720Sgblack@eecs.umich.edu case 2: 1107720Sgblack@eecs.umich.edu return packet->get<uint16_t>(); 1117720Sgblack@eecs.umich.edu 1127720Sgblack@eecs.umich.edu case 4: 1137720Sgblack@eecs.umich.edu return packet->get<uint32_t>(); 1142440SN/A 1152440SN/A case 8: 1165569Snate@binkert.org return packet->get<uint64_t>(); 117 118 default: 119 std::cerr << "bad store data size = " << packet->getSize() << std::endl; 120 121 assert(0); 122 return 0; 123 } 124 } 125 126 127}}; 128 129def template LoadStoreDeclare {{ 130 /** 131 * Static instruction class for "%(mnemonic)s". 132 */ 133 class %(class_name)s : public %(base_class)s 134 { 135 public: 136 137 /// Constructor. 138 %(class_name)s(ExtMachInst machInst); 139 140 %(BasicExecDeclare)s 141 142 %(EACompDeclare)s 143 144 %(InitiateAccDeclare)s 145 146 %(CompleteAccDeclare)s 147 }; 148}}; 149 150def template EACompDeclare {{ 151 Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 152}}; 153 154def template InitiateAccDeclare {{ 155 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 156}}; 157 158 159def template CompleteAccDeclare {{ 160 Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 161}}; 162 163def template LoadStoreConstructor {{ 164 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 165 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 166 { 167 %(constructor)s; 168 } 169}}; 170 171 172def template EACompExecute {{ 173 Fault 174 %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 175 Trace::InstRecord *traceData) const 176 { 177 Addr EA; 178 Fault fault = NoFault; 179 180 if (this->isFloating()) { 181 %(fp_enable_check)s; 182 183 if(fault != NoFault) 184 return fault; 185 } 186 187 %(op_decl)s; 188 %(op_rd)s; 189 %(ea_code)s; 190 191 // NOTE: Trace Data is written using execute or completeAcc templates 192 if (fault == NoFault) { 193 xc->setEA(EA); 194 } 195 196 return fault; 197 } 198}}; 199 200def template LoadExecute {{ 201 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 202 Trace::InstRecord *traceData) const 203 { 204 Addr EA; 205 Fault fault = NoFault; 206 207 if (this->isFloating()) { 208 %(fp_enable_check)s; 209 210 if(fault != NoFault) 211 return fault; 212 } 213 214 %(op_decl)s; 215 %(op_rd)s; 216 %(ea_code)s; 217 218 if (fault == NoFault) { 219 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 220 %(memacc_code)s; 221 } 222 223 if (fault == NoFault) { 224 %(op_wb)s; 225 } 226 227 return fault; 228 } 229}}; 230 231 232def template LoadInitiateAcc {{ 233 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 234 Trace::InstRecord *traceData) const 235 { 236 Addr EA; 237 Fault fault = NoFault; 238 239 if (this->isFloating()) { 240 %(fp_enable_check)s; 241 242 if(fault != NoFault) 243 return fault; 244 } 245 246 %(op_src_decl)s; 247 %(op_rd)s; 248 %(ea_code)s; 249 250 if (fault == NoFault) { 251 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 252 } 253 254 return fault; 255 } 256}}; 257 258def template LoadCompleteAcc {{ 259 Fault %(class_name)s::completeAcc(Packet *pkt, 260 %(CPU_exec_context)s *xc, 261 Trace::InstRecord *traceData) const 262 { 263 Fault fault = NoFault; 264 265 if (this->isFloating()) { 266 %(fp_enable_check)s; 267 268 if(fault != NoFault) 269 return fault; 270 } 271 272 %(op_decl)s; 273 %(op_rd)s; 274 275 Mem = pkt->get<typeof(Mem)>(); 276 277 if (fault == NoFault) { 278 %(memacc_code)s; 279 } 280 281 if (fault == NoFault) { 282 %(op_wb)s; 283 } 284 285 return fault; 286 } 287}}; 288 289def template StoreExecute {{ 290 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 291 Trace::InstRecord *traceData) const 292 { 293 Addr EA; 294 Fault fault = NoFault; 295 296 %(fp_enable_check)s; 297 %(op_decl)s; 298 %(op_rd)s; 299 %(ea_code)s; 300 301 if (fault == NoFault) { 302 %(memacc_code)s; 303 } 304 305 if (fault == NoFault) { 306 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 307 memAccessFlags, NULL); 308 } 309 310 if (fault == NoFault) { 311 %(postacc_code)s; 312 } 313 314 if (fault == NoFault) { 315 %(op_wb)s; 316 } 317 318 return fault; 319 } 320}}; 321 322 323def template StoreFPExecute {{ 324 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 325 Trace::InstRecord *traceData) const 326 { 327 Addr EA; 328 Fault fault = NoFault; 329 330 %(fp_enable_check)s; 331 if(fault != NoFault) 332 return fault; 333 %(op_decl)s; 334 %(op_rd)s; 335 %(ea_code)s; 336 337 if (fault == NoFault) { 338 %(memacc_code)s; 339 } 340 341 if (fault == NoFault) { 342 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 343 memAccessFlags, NULL); 344 } 345 346 if (fault == NoFault) { 347 %(postacc_code)s; 348 } 349 350 if (fault == NoFault) { 351 %(op_wb)s; 352 } 353 354 return fault; 355 } 356}}; 357 358def template StoreCondExecute {{ 359 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 360 Trace::InstRecord *traceData) const 361 { 362 Addr EA; 363 Fault fault = NoFault; 364 uint64_t write_result = 0; 365 366 %(fp_enable_check)s; 367 %(op_decl)s; 368 %(op_rd)s; 369 %(ea_code)s; 370 371 if (fault == NoFault) { 372 %(memacc_code)s; 373 } 374 375 if (fault == NoFault) { 376 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 377 memAccessFlags, &write_result); 378 } 379 380 if (fault == NoFault) { 381 %(postacc_code)s; 382 } 383 384 if (fault == NoFault) { 385 %(op_wb)s; 386 } 387 388 return fault; 389 } 390}}; 391 392def template StoreInitiateAcc {{ 393 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 394 Trace::InstRecord *traceData) const 395 { 396 Addr EA; 397 Fault fault = NoFault; 398 399 %(fp_enable_check)s; 400 %(op_decl)s; 401 %(op_rd)s; 402 %(ea_code)s; 403 404 if (fault == NoFault) { 405 %(memacc_code)s; 406 } 407 408 if (fault == NoFault) { 409 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 410 memAccessFlags, NULL); 411 } 412 413 return fault; 414 } 415}}; 416 417 418def template StoreCompleteAcc {{ 419 Fault %(class_name)s::completeAcc(Packet *pkt, 420 %(CPU_exec_context)s *xc, 421 Trace::InstRecord *traceData) const 422 { 423 return NoFault; 424 } 425}}; 426 427def template StoreCondCompleteAcc {{ 428 Fault %(class_name)s::completeAcc(Packet *pkt, 429 %(CPU_exec_context)s *xc, 430 Trace::InstRecord *traceData) const 431 { 432 Fault fault = NoFault; 433 434 %(fp_enable_check)s; 435 %(op_dest_decl)s; 436 437 uint64_t write_result = pkt->req->getExtraData(); 438 439 if (fault == NoFault) { 440 %(postacc_code)s; 441 } 442 443 if (fault == NoFault) { 444 %(op_wb)s; 445 } 446 447 return fault; 448 } 449}}; 450 451def template MiscExecute {{ 452 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 453 Trace::InstRecord *traceData) const 454 { 455 Addr EA; 456 Fault fault = NoFault; 457 458 %(fp_enable_check)s; 459 %(op_decl)s; 460 %(op_rd)s; 461 %(ea_code)s; 462 463 if (fault == NoFault) { 464 %(memacc_code)s; 465 } 466 467 return NoFault; 468 } 469}}; 470 471def template MiscInitiateAcc {{ 472 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 473 Trace::InstRecord *traceData) const 474 { 475 panic("Misc instruction does not support split access method!"); 476 return NoFault; 477 } 478}}; 479 480 481def template MiscCompleteAcc {{ 482 Fault %(class_name)s::completeAcc(Packet *pkt, 483 %(CPU_exec_context)s *xc, 484 Trace::InstRecord *traceData) const 485 { 486 panic("Misc instruction does not support split access method!"); 487 488 return NoFault; 489 } 490}}; 491 492def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 493 mem_flags = [], inst_flags = []) {{ 494 (header_output, decoder_output, decode_block, exec_output) = \ 495 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 496 decode_template = ImmNopCheckDecode, 497 exec_template_base = 'Load') 498}}; 499 500 501def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 502 mem_flags = [], inst_flags = []) {{ 503 (header_output, decoder_output, decode_block, exec_output) = \ 504 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 505 exec_template_base = 'Store') 506}}; 507 508def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 509 mem_flags = [], inst_flags = []) {{ 510 inst_flags += ['IsIndexed'] 511 (header_output, decoder_output, decode_block, exec_output) = \ 512 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 513 decode_template = ImmNopCheckDecode, 514 exec_template_base = 'Load') 515}}; 516 517def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 518 mem_flags = [], inst_flags = []) {{ 519 inst_flags += ['IsIndexed'] 520 (header_output, decoder_output, decode_block, exec_output) = \ 521 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 522 exec_template_base = 'Store') 523}}; 524 525def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 526 mem_flags = [], inst_flags = []) {{ 527 inst_flags += ['IsIndexed', 'IsFloating'] 528 (header_output, decoder_output, decode_block, exec_output) = \ 529 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 530 decode_template = ImmNopCheckDecode, 531 exec_template_base = 'Load') 532}}; 533 534def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 535 mem_flags = [], inst_flags = []) {{ 536 inst_flags += ['IsIndexed', 'IsFloating'] 537 (header_output, decoder_output, decode_block, exec_output) = \ 538 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 539 exec_template_base = 'Store') 540}}; 541 542 543def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 544 mem_flags = [], inst_flags = []) {{ 545 decl_code = 'uint32_t mem_word = Mem.uw;\n' 546 decl_code += 'uint32_t unalign_addr = Rs + disp;\n' 547 decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n' 548 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 549 decl_code += '\tbyte_offset ^= 3;\n' 550 decl_code += '#endif\n' 551 552 memacc_code = decl_code + memacc_code 553 554 (header_output, decoder_output, decode_block, exec_output) = \ 555 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 556 decode_template = ImmNopCheckDecode, 557 exec_template_base = 'Load') 558}}; 559 560def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 561 mem_flags = [], inst_flags = []) {{ 562 decl_code = 'uint32_t mem_word = 0;\n' 563 decl_code += 'uint32_t unaligned_addr = Rs + disp;\n' 564 decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n' 565 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 566 decl_code += '\tbyte_offset ^= 3;\n' 567 decl_code += '#endif\n' 568 decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n' 569 #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);' 570 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 571 572 (header_output, decoder_output, decode_block, exec_output) = \ 573 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 574 exec_template_base = 'Store') 575}}; 576 577def format Prefetch(ea_code = {{ EA = Rs + disp; }}, 578 mem_flags = [], pf_flags = [], inst_flags = []) {{ 579 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 580 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 581 'IsDataPrefetch', 'MemReadOp'] 582 583 (header_output, decoder_output, decode_block, exec_output) = \ 584 LoadStoreBase(name, Name, ea_code, 585 'xc->prefetch(EA, memAccessFlags);', 586 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 587 588}}; 589 590def format StoreCond(memacc_code, postacc_code, 591 ea_code = {{ EA = Rs + disp; }}, 592 mem_flags = [], inst_flags = []) {{ 593 (header_output, decoder_output, decode_block, exec_output) = \ 594 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 595 postacc_code, exec_template_base = 'StoreCond') 596}}; 597