mem.isa revision 6207
12124SN/A// -*- mode:c++ -*- 22124SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Steve Reinhardt 305268Sksewell@umich.edu// Korey Sewell 312022SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342706Sksewell@umich.edu// Memory-format instructions 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372022SN/Aoutput header {{ 382124SN/A /** 392124SN/A * Base class for general Mips memory-format instructions. 402124SN/A */ 412124SN/A class Memory : public MipsStaticInst 422124SN/A { 432124SN/A protected: 442124SN/A /// Memory request flags. See mem_req_base.hh. 455736Snate@binkert.org Request::Flags memAccessFlags; 462239SN/A 472124SN/A /// Displacement for EA calculation (signed). 482124SN/A int32_t disp; 492124SN/A 502124SN/A /// Constructor 516207Sksewell@umich.edu Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 522124SN/A : MipsStaticInst(mnem, _machInst, __opClass), 532742Sksewell@umich.edu disp(sext<16>(OFFSET)) 542022SN/A { 552124SN/A } 562022SN/A 572124SN/A std::string 582124SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 592124SN/A }; 602124SN/A 612742Sksewell@umich.edu /** 622742Sksewell@umich.edu * Base class for a few miscellaneous memory-format insts 632742Sksewell@umich.edu * that don't interpret the disp field 642742Sksewell@umich.edu */ 652742Sksewell@umich.edu class MemoryNoDisp : public Memory 662742Sksewell@umich.edu { 672742Sksewell@umich.edu protected: 682742Sksewell@umich.edu /// Constructor 696207Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 706207Sksewell@umich.edu : Memory(mnem, _machInst, __opClass) 712742Sksewell@umich.edu { 722742Sksewell@umich.edu } 732742Sksewell@umich.edu 742742Sksewell@umich.edu std::string 752742Sksewell@umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 762742Sksewell@umich.edu }; 772022SN/A}}; 782022SN/A 792124SN/A 802022SN/Aoutput decoder {{ 812124SN/A std::string 822124SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 832124SN/A { 842742Sksewell@umich.edu return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 852239SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 862124SN/A } 872124SN/A 882742Sksewell@umich.edu std::string 892742Sksewell@umich.edu MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 902742Sksewell@umich.edu { 912742Sksewell@umich.edu return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 922742Sksewell@umich.edu flags[IsFloating] ? 'f' : 'r', 932742Sksewell@umich.edu flags[IsFloating] ? FD : RD, 942742Sksewell@umich.edu RS, RT); 952742Sksewell@umich.edu } 964661Sksewell@umich.edu 974661Sksewell@umich.edu}}; 984661Sksewell@umich.edu 994661Sksewell@umich.eduoutput exec {{ 1004661Sksewell@umich.edu /** return data in cases where there the size of data is only 1014661Sksewell@umich.edu known in the packet 1024661Sksewell@umich.edu */ 1035222Sksewell@umich.edu uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) { 1044661Sksewell@umich.edu switch (packet->getSize()) 1054661Sksewell@umich.edu { 1065222Sksewell@umich.edu case 1: 1074661Sksewell@umich.edu return packet->get<uint8_t>(); 1084661Sksewell@umich.edu 1095222Sksewell@umich.edu case 2: 1104661Sksewell@umich.edu return packet->get<uint16_t>(); 1114661Sksewell@umich.edu 1125222Sksewell@umich.edu case 4: 1134661Sksewell@umich.edu return packet->get<uint32_t>(); 1144661Sksewell@umich.edu 1155222Sksewell@umich.edu case 8: 1164661Sksewell@umich.edu return packet->get<uint64_t>(); 1174661Sksewell@umich.edu 1184661Sksewell@umich.edu default: 1194661Sksewell@umich.edu std::cerr << "bad store data size = " << packet->getSize() << std::endl; 1204661Sksewell@umich.edu 1214661Sksewell@umich.edu assert(0); 1224661Sksewell@umich.edu return 0; 1234661Sksewell@umich.edu } 1244661Sksewell@umich.edu } 1254661Sksewell@umich.edu 1264661Sksewell@umich.edu 1272022SN/A}}; 1282022SN/A 1292124SN/Adef template LoadStoreDeclare {{ 1302124SN/A /** 1312124SN/A * Static instruction class for "%(mnemonic)s". 1322124SN/A */ 1332124SN/A class %(class_name)s : public %(base_class)s 1342124SN/A { 1352124SN/A public: 1362124SN/A 1372124SN/A /// Constructor. 1384661Sksewell@umich.edu %(class_name)s(ExtMachInst machInst); 1392124SN/A 1402124SN/A %(BasicExecDeclare)s 1412124SN/A 1426207Sksewell@umich.edu %(EACompDeclare)s 1436207Sksewell@umich.edu 1442124SN/A %(InitiateAccDeclare)s 1452124SN/A 1462124SN/A %(CompleteAccDeclare)s 1472124SN/A }; 1482022SN/A}}; 1492022SN/A 1506207Sksewell@umich.edudef template EACompDeclare {{ 1516207Sksewell@umich.edu Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1526207Sksewell@umich.edu}}; 1532124SN/A 1542124SN/Adef template InitiateAccDeclare {{ 1552132SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1562022SN/A}}; 1572124SN/A 1582124SN/A 1592124SN/Adef template CompleteAccDeclare {{ 1604661Sksewell@umich.edu Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1612124SN/A}}; 1622124SN/A 1636207Sksewell@umich.edudef template LoadStoreConstructor {{ 1646207Sksewell@umich.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1656207Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1662124SN/A { 1673953Sstever@eecs.umich.edu %(constructor)s; 1682124SN/A } 1693953Sstever@eecs.umich.edu}}; 1702124SN/A 1713953Sstever@eecs.umich.edu 1722124SN/Adef template EACompExecute {{ 1732132SN/A Fault 1746207Sksewell@umich.edu %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 1752124SN/A Trace::InstRecord *traceData) const 1762124SN/A { 1772124SN/A Addr EA; 1782132SN/A Fault fault = NoFault; 1792124SN/A 1805222Sksewell@umich.edu if (this->isFloating()) { 1815222Sksewell@umich.edu %(fp_enable_check)s; 1825222Sksewell@umich.edu 1835222Sksewell@umich.edu if(fault != NoFault) 1845222Sksewell@umich.edu return fault; 1855222Sksewell@umich.edu } 1865222Sksewell@umich.edu 1872124SN/A %(op_decl)s; 1882124SN/A %(op_rd)s; 1893953Sstever@eecs.umich.edu %(ea_code)s; 1902124SN/A 1914661Sksewell@umich.edu // NOTE: Trace Data is written using execute or completeAcc templates 1922124SN/A if (fault == NoFault) { 1932124SN/A xc->setEA(EA); 1942124SN/A } 1952124SN/A 1962124SN/A return fault; 1972124SN/A } 1982124SN/A}}; 1992124SN/A 2002124SN/Adef template LoadExecute {{ 2012132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2022124SN/A Trace::InstRecord *traceData) const 2032124SN/A { 2042124SN/A Addr EA; 2052132SN/A Fault fault = NoFault; 2062124SN/A 2075222Sksewell@umich.edu if (this->isFloating()) { 2085222Sksewell@umich.edu %(fp_enable_check)s; 2095222Sksewell@umich.edu 2105222Sksewell@umich.edu if(fault != NoFault) 2115222Sksewell@umich.edu return fault; 2125222Sksewell@umich.edu } 2135222Sksewell@umich.edu 2142124SN/A %(op_decl)s; 2152124SN/A %(op_rd)s; 2162124SN/A %(ea_code)s; 2172124SN/A 2182124SN/A if (fault == NoFault) { 2192124SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 2202124SN/A %(memacc_code)s; 2212124SN/A } 2222124SN/A 2232124SN/A if (fault == NoFault) { 2242124SN/A %(op_wb)s; 2252124SN/A } 2262124SN/A 2272124SN/A return fault; 2282124SN/A } 2292124SN/A}}; 2302124SN/A 2312124SN/A 2322124SN/Adef template LoadInitiateAcc {{ 2332132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2342124SN/A Trace::InstRecord *traceData) const 2352124SN/A { 2362239SN/A Addr EA; 2372132SN/A Fault fault = NoFault; 2382239SN/A 2395222Sksewell@umich.edu if (this->isFloating()) { 2405222Sksewell@umich.edu %(fp_enable_check)s; 2415222Sksewell@umich.edu 2425222Sksewell@umich.edu if(fault != NoFault) 2435222Sksewell@umich.edu return fault; 2445222Sksewell@umich.edu } 2455222Sksewell@umich.edu 2462239SN/A %(op_src_decl)s; 2472239SN/A %(op_rd)s; 2482239SN/A %(ea_code)s; 2492239SN/A 2502239SN/A if (fault == NoFault) { 2512239SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 2522239SN/A } 2532239SN/A 2542124SN/A return fault; 2552124SN/A } 2562124SN/A}}; 2572124SN/A 2582124SN/Adef template LoadCompleteAcc {{ 2594661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 2602124SN/A %(CPU_exec_context)s *xc, 2612124SN/A Trace::InstRecord *traceData) const 2622124SN/A { 2632132SN/A Fault fault = NoFault; 2642239SN/A 2655222Sksewell@umich.edu if (this->isFloating()) { 2665222Sksewell@umich.edu %(fp_enable_check)s; 2675222Sksewell@umich.edu 2685222Sksewell@umich.edu if(fault != NoFault) 2695222Sksewell@umich.edu return fault; 2705222Sksewell@umich.edu } 2715222Sksewell@umich.edu 2722506SN/A %(op_decl)s; 2734661Sksewell@umich.edu %(op_rd)s; 2742239SN/A 2752935Sksewell@umich.edu Mem = pkt->get<typeof(Mem)>(); 2762239SN/A 2772239SN/A if (fault == NoFault) { 2782239SN/A %(memacc_code)s; 2792239SN/A } 2802239SN/A 2812239SN/A if (fault == NoFault) { 2822239SN/A %(op_wb)s; 2832239SN/A } 2842239SN/A 2852124SN/A return fault; 2862124SN/A } 2872124SN/A}}; 2882124SN/A 2892124SN/Adef template StoreExecute {{ 2902132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2912124SN/A Trace::InstRecord *traceData) const 2922124SN/A { 2932124SN/A Addr EA; 2942132SN/A Fault fault = NoFault; 2954056Sstever@eecs.umich.edu 2964056Sstever@eecs.umich.edu %(fp_enable_check)s; 2974056Sstever@eecs.umich.edu %(op_decl)s; 2984056Sstever@eecs.umich.edu %(op_rd)s; 2994056Sstever@eecs.umich.edu %(ea_code)s; 3004056Sstever@eecs.umich.edu 3014056Sstever@eecs.umich.edu if (fault == NoFault) { 3024056Sstever@eecs.umich.edu %(memacc_code)s; 3034056Sstever@eecs.umich.edu } 3044056Sstever@eecs.umich.edu 3054056Sstever@eecs.umich.edu if (fault == NoFault) { 3064056Sstever@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3074675Sksewell@umich.edu memAccessFlags, NULL); 3084056Sstever@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 3094056Sstever@eecs.umich.edu } 3104056Sstever@eecs.umich.edu 3114056Sstever@eecs.umich.edu if (fault == NoFault) { 3124056Sstever@eecs.umich.edu %(postacc_code)s; 3134056Sstever@eecs.umich.edu } 3144056Sstever@eecs.umich.edu 3154056Sstever@eecs.umich.edu if (fault == NoFault) { 3164056Sstever@eecs.umich.edu %(op_wb)s; 3174056Sstever@eecs.umich.edu } 3184056Sstever@eecs.umich.edu 3194056Sstever@eecs.umich.edu return fault; 3204056Sstever@eecs.umich.edu } 3214056Sstever@eecs.umich.edu}}; 3224056Sstever@eecs.umich.edu 3235222Sksewell@umich.edu 3245222Sksewell@umich.edudef template StoreFPExecute {{ 3255222Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3265222Sksewell@umich.edu Trace::InstRecord *traceData) const 3275222Sksewell@umich.edu { 3285222Sksewell@umich.edu Addr EA; 3295222Sksewell@umich.edu Fault fault = NoFault; 3305222Sksewell@umich.edu 3315222Sksewell@umich.edu %(fp_enable_check)s; 3325222Sksewell@umich.edu if(fault != NoFault) 3335222Sksewell@umich.edu return fault; 3345222Sksewell@umich.edu %(op_decl)s; 3355222Sksewell@umich.edu %(op_rd)s; 3365222Sksewell@umich.edu %(ea_code)s; 3375222Sksewell@umich.edu 3385222Sksewell@umich.edu if (fault == NoFault) { 3395222Sksewell@umich.edu %(memacc_code)s; 3405222Sksewell@umich.edu } 3415222Sksewell@umich.edu 3425222Sksewell@umich.edu if (fault == NoFault) { 3435222Sksewell@umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3445222Sksewell@umich.edu memAccessFlags, NULL); 3455222Sksewell@umich.edu if (traceData) { traceData->setData(Mem); } 3465222Sksewell@umich.edu } 3475222Sksewell@umich.edu 3485222Sksewell@umich.edu if (fault == NoFault) { 3495222Sksewell@umich.edu %(postacc_code)s; 3505222Sksewell@umich.edu } 3515222Sksewell@umich.edu 3525222Sksewell@umich.edu if (fault == NoFault) { 3535222Sksewell@umich.edu %(op_wb)s; 3545222Sksewell@umich.edu } 3555222Sksewell@umich.edu 3565222Sksewell@umich.edu return fault; 3575222Sksewell@umich.edu } 3585222Sksewell@umich.edu}}; 3595222Sksewell@umich.edu 3604056Sstever@eecs.umich.edudef template StoreCondExecute {{ 3614056Sstever@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3624056Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 3634056Sstever@eecs.umich.edu { 3644056Sstever@eecs.umich.edu Addr EA; 3654056Sstever@eecs.umich.edu Fault fault = NoFault; 3662124SN/A uint64_t write_result = 0; 3672124SN/A 3682124SN/A %(fp_enable_check)s; 3692124SN/A %(op_decl)s; 3702124SN/A %(op_rd)s; 3712124SN/A %(ea_code)s; 3722124SN/A 3732124SN/A if (fault == NoFault) { 3742124SN/A %(memacc_code)s; 3752124SN/A } 3762124SN/A 3772124SN/A if (fault == NoFault) { 3782124SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3792124SN/A memAccessFlags, &write_result); 3802124SN/A if (traceData) { traceData->setData(Mem); } 3812124SN/A } 3822124SN/A 3832124SN/A if (fault == NoFault) { 3842124SN/A %(postacc_code)s; 3852124SN/A } 3862124SN/A 3872124SN/A if (fault == NoFault) { 3882124SN/A %(op_wb)s; 3892124SN/A } 3902124SN/A 3912124SN/A return fault; 3922124SN/A } 3932124SN/A}}; 3942124SN/A 3952124SN/Adef template StoreInitiateAcc {{ 3962132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3972124SN/A Trace::InstRecord *traceData) const 3982124SN/A { 3992239SN/A Addr EA; 4002132SN/A Fault fault = NoFault; 4012239SN/A 4022239SN/A %(fp_enable_check)s; 4032506SN/A %(op_decl)s; 4042239SN/A %(op_rd)s; 4052239SN/A %(ea_code)s; 4062239SN/A 4072239SN/A if (fault == NoFault) { 4082239SN/A %(memacc_code)s; 4092239SN/A } 4102239SN/A 4112239SN/A if (fault == NoFault) { 4122239SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 4132935Sksewell@umich.edu memAccessFlags, NULL); 4142239SN/A if (traceData) { traceData->setData(Mem); } 4152239SN/A } 4162239SN/A 4172124SN/A return fault; 4182124SN/A } 4192124SN/A}}; 4202124SN/A 4212124SN/A 4222124SN/Adef template StoreCompleteAcc {{ 4234661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 4242124SN/A %(CPU_exec_context)s *xc, 4252124SN/A Trace::InstRecord *traceData) const 4262124SN/A { 4272132SN/A Fault fault = NoFault; 4282239SN/A 4292239SN/A %(fp_enable_check)s; 4302239SN/A %(op_dest_decl)s; 4312239SN/A 4322935Sksewell@umich.edu if (fault == NoFault) { 4332935Sksewell@umich.edu %(postacc_code)s; 4342935Sksewell@umich.edu } 4352935Sksewell@umich.edu 4362935Sksewell@umich.edu if (fault == NoFault) { 4372935Sksewell@umich.edu %(op_wb)s; 4384661Sksewell@umich.edu 4395222Sksewell@umich.edu if (traceData) { traceData->setData(getMemData(xc, pkt)); } 4405222Sksewell@umich.edu } 4415222Sksewell@umich.edu 4425222Sksewell@umich.edu return fault; 4435222Sksewell@umich.edu } 4445222Sksewell@umich.edu}}; 4455222Sksewell@umich.edu 4465222Sksewell@umich.edu 4475222Sksewell@umich.edudef template StoreCompleteAcc {{ 4485222Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 4495222Sksewell@umich.edu %(CPU_exec_context)s *xc, 4505222Sksewell@umich.edu Trace::InstRecord *traceData) const 4515222Sksewell@umich.edu { 4525222Sksewell@umich.edu Fault fault = NoFault; 4535222Sksewell@umich.edu 4545222Sksewell@umich.edu %(op_dest_decl)s; 4555222Sksewell@umich.edu 4565222Sksewell@umich.edu if (fault == NoFault) { 4575222Sksewell@umich.edu %(postacc_code)s; 4585222Sksewell@umich.edu } 4595222Sksewell@umich.edu 4605222Sksewell@umich.edu if (fault == NoFault) { 4615222Sksewell@umich.edu %(op_wb)s; 4625222Sksewell@umich.edu 4635222Sksewell@umich.edu if (traceData) { traceData->setData(getMemData(xc, pkt)); } 4642935Sksewell@umich.edu } 4652935Sksewell@umich.edu 4662935Sksewell@umich.edu return fault; 4672935Sksewell@umich.edu } 4682935Sksewell@umich.edu}}; 4692935Sksewell@umich.edu 4702935Sksewell@umich.edudef template StoreCondCompleteAcc {{ 4714661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 4722935Sksewell@umich.edu %(CPU_exec_context)s *xc, 4732935Sksewell@umich.edu Trace::InstRecord *traceData) const 4742935Sksewell@umich.edu { 4752935Sksewell@umich.edu Fault fault = NoFault; 4762935Sksewell@umich.edu 4772935Sksewell@umich.edu %(fp_enable_check)s; 4782935Sksewell@umich.edu %(op_dest_decl)s; 4792935Sksewell@umich.edu 4804055Ssaidi@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 4812239SN/A 4822239SN/A if (fault == NoFault) { 4832239SN/A %(postacc_code)s; 4842239SN/A } 4852239SN/A 4862239SN/A if (fault == NoFault) { 4872239SN/A %(op_wb)s; 4882239SN/A } 4892239SN/A 4902124SN/A return fault; 4912124SN/A } 4922124SN/A}}; 4932124SN/A 4942686Sksewell@umich.edudef template MiscExecute {{ 4952686Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 4962686Sksewell@umich.edu Trace::InstRecord *traceData) const 4972686Sksewell@umich.edu { 4982686Sksewell@umich.edu Addr EA; 4992686Sksewell@umich.edu Fault fault = NoFault; 5002686Sksewell@umich.edu 5012686Sksewell@umich.edu %(fp_enable_check)s; 5022686Sksewell@umich.edu %(op_decl)s; 5032686Sksewell@umich.edu %(op_rd)s; 5042686Sksewell@umich.edu %(ea_code)s; 5052686Sksewell@umich.edu 5062686Sksewell@umich.edu if (fault == NoFault) { 5072686Sksewell@umich.edu %(memacc_code)s; 5082686Sksewell@umich.edu } 5092686Sksewell@umich.edu 5102686Sksewell@umich.edu return NoFault; 5112686Sksewell@umich.edu } 5122686Sksewell@umich.edu}}; 5132686Sksewell@umich.edu 5142686Sksewell@umich.edudef template MiscInitiateAcc {{ 5152686Sksewell@umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 5162686Sksewell@umich.edu Trace::InstRecord *traceData) const 5172686Sksewell@umich.edu { 5182686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 5192686Sksewell@umich.edu return NoFault; 5202686Sksewell@umich.edu } 5212686Sksewell@umich.edu}}; 5222686Sksewell@umich.edu 5232686Sksewell@umich.edu 5242686Sksewell@umich.edudef template MiscCompleteAcc {{ 5254661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 5262686Sksewell@umich.edu %(CPU_exec_context)s *xc, 5272686Sksewell@umich.edu Trace::InstRecord *traceData) const 5282686Sksewell@umich.edu { 5292686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 5302686Sksewell@umich.edu 5312686Sksewell@umich.edu return NoFault; 5322686Sksewell@umich.edu } 5332686Sksewell@umich.edu}}; 5342686Sksewell@umich.edu 5352124SN/Adef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 5362124SN/A mem_flags = [], inst_flags = []) {{ 5372124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5382124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5392750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5402124SN/A exec_template_base = 'Load') 5412124SN/A}}; 5422124SN/A 5435222Sksewell@umich.edu 5442124SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 5452124SN/A mem_flags = [], inst_flags = []) {{ 5462124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5472124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5482124SN/A exec_template_base = 'Store') 5492124SN/A}}; 5502124SN/A 5512686Sksewell@umich.edudef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5522573SN/A mem_flags = [], inst_flags = []) {{ 5535222Sksewell@umich.edu inst_flags += ['IsIndexed'] 5542573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5552573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5562750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5572573SN/A exec_template_base = 'Load') 5582573SN/A}}; 5592573SN/A 5602686Sksewell@umich.edudef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5612573SN/A mem_flags = [], inst_flags = []) {{ 5625222Sksewell@umich.edu inst_flags += ['IsIndexed'] 5632573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5642573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5652573SN/A exec_template_base = 'Store') 5662573SN/A}}; 5672573SN/A 5685222Sksewell@umich.edudef format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5695222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5705222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 5715222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5725222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5735222Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5745222Sksewell@umich.edu exec_template_base = 'Load') 5755222Sksewell@umich.edu}}; 5765222Sksewell@umich.edu 5775222Sksewell@umich.edudef format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5785222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5795222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 5805222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5815222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5825222Sksewell@umich.edu exec_template_base = 'Store') 5835222Sksewell@umich.edu}}; 5845222Sksewell@umich.edu 5855222Sksewell@umich.edu 5862686Sksewell@umich.edudef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5872686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5882686Sksewell@umich.edu decl_code = 'uint32_t mem_word = Mem.uw;\n' 5892686Sksewell@umich.edu decl_code += 'uint32_t unalign_addr = Rs + disp;\n' 5902686Sksewell@umich.edu decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n' 5912686Sksewell@umich.edu decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 5922686Sksewell@umich.edu decl_code += '\tbyte_offset ^= 3;\n' 5932686Sksewell@umich.edu decl_code += '#endif\n' 5942573SN/A 5952686Sksewell@umich.edu memacc_code = decl_code + memacc_code 5962686Sksewell@umich.edu 5972686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5982686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5992750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 6002686Sksewell@umich.edu exec_template_base = 'Load') 6012686Sksewell@umich.edu}}; 6022686Sksewell@umich.edu 6032686Sksewell@umich.edudef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 6042686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 6052686Sksewell@umich.edu decl_code = 'uint32_t mem_word = 0;\n' 6062686Sksewell@umich.edu decl_code += 'uint32_t unaligned_addr = Rs + disp;\n' 6072686Sksewell@umich.edu decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n' 6082686Sksewell@umich.edu decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 6092686Sksewell@umich.edu decl_code += '\tbyte_offset ^= 3;\n' 6102686Sksewell@umich.edu decl_code += '#endif\n' 6112686Sksewell@umich.edu decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n' 6124661Sksewell@umich.edu #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);' 6132686Sksewell@umich.edu memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 6142686Sksewell@umich.edu 6152686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 6162686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 6172686Sksewell@umich.edu exec_template_base = 'Store') 6182686Sksewell@umich.edu}}; 6192686Sksewell@umich.edu 6202686Sksewell@umich.edudef format Prefetch(ea_code = {{ EA = Rs + disp; }}, 6212686Sksewell@umich.edu mem_flags = [], pf_flags = [], inst_flags = []) {{ 6222686Sksewell@umich.edu pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT'] 6232686Sksewell@umich.edu pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 6242686Sksewell@umich.edu 'IsDataPrefetch', 'MemReadOp'] 6252686Sksewell@umich.edu 6262686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 6272686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, 6282686Sksewell@umich.edu 'xc->prefetch(EA, memAccessFlags);', 6292686Sksewell@umich.edu pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 6302686Sksewell@umich.edu 6312686Sksewell@umich.edu}}; 6322686Sksewell@umich.edu 6332686Sksewell@umich.edudef format StoreCond(memacc_code, postacc_code, 6342686Sksewell@umich.edu ea_code = {{ EA = Rs + disp; }}, 6352495SN/A mem_flags = [], inst_flags = []) {{ 6362495SN/A (header_output, decoder_output, decode_block, exec_output) = \ 6372495SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 6382935Sksewell@umich.edu postacc_code, exec_template_base = 'StoreCond') 6392495SN/A}}; 640