mem.isa revision 4675
12124SN/A// -*- mode:c++ -*-
22124SN/A
32754Sksewell@umich.edu// Copyright (c) 2006 The Regents of The University of Michigan
42124SN/A// All rights reserved.
52022SN/A//
62124SN/A// Redistribution and use in source and binary forms, with or without
72124SN/A// modification, are permitted provided that the following conditions are
82124SN/A// met: redistributions of source code must retain the above copyright
92124SN/A// notice, this list of conditions and the following disclaimer;
102124SN/A// redistributions in binary form must reproduce the above copyright
112124SN/A// notice, this list of conditions and the following disclaimer in the
122124SN/A// documentation and/or other materials provided with the distribution;
132124SN/A// neither the name of the copyright holders nor the names of its
142124SN/A// contributors may be used to endorse or promote products derived from
152124SN/A// this software without specific prior written permission.
162022SN/A//
172124SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182124SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192124SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202124SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212124SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222124SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232124SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242124SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252124SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262124SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272124SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282665Ssaidi@eecs.umich.edu//
292935Sksewell@umich.edu// Authors: Steve Reinhardt
302665Ssaidi@eecs.umich.edu//          Korey Sewell
312022SN/A
322649Ssaidi@eecs.umich.edu////////////////////////////////////////////////////////////////////
332649Ssaidi@eecs.umich.edu//
342706Sksewell@umich.edu// Memory-format instructions
352649Ssaidi@eecs.umich.edu//
362649Ssaidi@eecs.umich.edu
372022SN/Aoutput header {{
382124SN/A    /**
392124SN/A     * Base class for general Mips memory-format instructions.
402124SN/A     */
412124SN/A    class Memory : public MipsStaticInst
422124SN/A    {
432124SN/A      protected:
442124SN/A
452124SN/A        /// Memory request flags.  See mem_req_base.hh.
462124SN/A        unsigned memAccessFlags;
472124SN/A        /// Pointer to EAComp object.
482124SN/A        const StaticInstPtr eaCompPtr;
492124SN/A        /// Pointer to MemAcc object.
502124SN/A        const StaticInstPtr memAccPtr;
512239SN/A
522124SN/A        /// Displacement for EA calculation (signed).
532124SN/A        int32_t disp;
542124SN/A
552124SN/A        /// Constructor
562124SN/A        Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
572124SN/A               StaticInstPtr _eaCompPtr = nullStaticInstPtr,
582124SN/A               StaticInstPtr _memAccPtr = nullStaticInstPtr)
592124SN/A            : MipsStaticInst(mnem, _machInst, __opClass),
602124SN/A              memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr),
612742Sksewell@umich.edu              disp(sext<16>(OFFSET))
622022SN/A        {
632124SN/A        }
642022SN/A
652124SN/A        std::string
662124SN/A        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
672022SN/A
682124SN/A      public:
692124SN/A
702124SN/A        const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
712124SN/A        const StaticInstPtr &memAccInst() const { return memAccPtr; }
724661Sksewell@umich.edu
734661Sksewell@umich.edu        unsigned memAccFlags() { return memAccessFlags; }
742124SN/A    };
752124SN/A
762742Sksewell@umich.edu     /**
772742Sksewell@umich.edu     * Base class for a few miscellaneous memory-format insts
782742Sksewell@umich.edu     * that don't interpret the disp field
792742Sksewell@umich.edu     */
802742Sksewell@umich.edu    class MemoryNoDisp : public Memory
812742Sksewell@umich.edu    {
822742Sksewell@umich.edu      protected:
832742Sksewell@umich.edu        /// Constructor
842742Sksewell@umich.edu        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
852742Sksewell@umich.edu                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
862742Sksewell@umich.edu                     StaticInstPtr _memAccPtr = nullStaticInstPtr)
872742Sksewell@umich.edu            : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
882742Sksewell@umich.edu        {
892742Sksewell@umich.edu        }
902742Sksewell@umich.edu
912742Sksewell@umich.edu        std::string
922742Sksewell@umich.edu        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
932742Sksewell@umich.edu    };
942022SN/A}};
952022SN/A
962124SN/A
972022SN/Aoutput decoder {{
982124SN/A    std::string
992124SN/A    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1002124SN/A    {
1012742Sksewell@umich.edu        return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
1022239SN/A                        flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
1032124SN/A    }
1042124SN/A
1052742Sksewell@umich.edu    std::string
1062742Sksewell@umich.edu    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
1072742Sksewell@umich.edu    {
1082742Sksewell@umich.edu        return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
1092742Sksewell@umich.edu                        flags[IsFloating] ? 'f' : 'r',
1102742Sksewell@umich.edu                        flags[IsFloating] ? FD : RD,
1112742Sksewell@umich.edu                        RS, RT);
1122742Sksewell@umich.edu    }
1134661Sksewell@umich.edu
1144661Sksewell@umich.edu}};
1154661Sksewell@umich.edu
1164661Sksewell@umich.eduoutput exec {{
1174661Sksewell@umich.edu    /** return data in cases where there the size of data is only
1184661Sksewell@umich.edu        known in the packet
1194661Sksewell@umich.edu    */
1204673Sksewell@umich.edu    uint64_t getStoreData(%(CPU_exec_context)s *xc, Packet *packet) {
1214661Sksewell@umich.edu        switch (packet->getSize())
1224661Sksewell@umich.edu        {
1234661Sksewell@umich.edu          case 8:
1244661Sksewell@umich.edu            return packet->get<uint8_t>();
1254661Sksewell@umich.edu
1264661Sksewell@umich.edu          case 16:
1274661Sksewell@umich.edu            return packet->get<uint16_t>();
1284661Sksewell@umich.edu
1294661Sksewell@umich.edu          case 32:
1304661Sksewell@umich.edu            return packet->get<uint32_t>();
1314661Sksewell@umich.edu
1324661Sksewell@umich.edu          case 864:
1334661Sksewell@umich.edu            return packet->get<uint64_t>();
1344661Sksewell@umich.edu
1354661Sksewell@umich.edu          default:
1364661Sksewell@umich.edu            std::cerr << "bad store data size = " << packet->getSize() << std::endl;
1374661Sksewell@umich.edu
1384661Sksewell@umich.edu            assert(0);
1394661Sksewell@umich.edu            return 0;
1404661Sksewell@umich.edu        }
1414661Sksewell@umich.edu    }
1424661Sksewell@umich.edu
1434661Sksewell@umich.edu
1442022SN/A}};
1452022SN/A
1462124SN/Adef template LoadStoreDeclare {{
1472124SN/A    /**
1482124SN/A     * Static instruction class for "%(mnemonic)s".
1492124SN/A     */
1502124SN/A    class %(class_name)s : public %(base_class)s
1512124SN/A    {
1522124SN/A      protected:
1532124SN/A
1542124SN/A        /**
1552124SN/A         * "Fake" effective address computation class for "%(mnemonic)s".
1562124SN/A         */
1572124SN/A        class EAComp : public %(base_class)s
1582124SN/A        {
1592124SN/A          public:
1602124SN/A            /// Constructor
1614661Sksewell@umich.edu            EAComp(ExtMachInst machInst);
1622124SN/A
1632124SN/A            %(BasicExecDeclare)s
1642124SN/A        };
1652124SN/A
1662124SN/A        /**
1672124SN/A         * "Fake" memory access instruction class for "%(mnemonic)s".
1682124SN/A         */
1692124SN/A        class MemAcc : public %(base_class)s
1702124SN/A        {
1712124SN/A          public:
1722124SN/A            /// Constructor
1734661Sksewell@umich.edu            MemAcc(ExtMachInst machInst);
1742124SN/A
1752124SN/A            %(BasicExecDeclare)s
1762124SN/A        };
1772124SN/A
1782124SN/A      public:
1792124SN/A
1802124SN/A        /// Constructor.
1814661Sksewell@umich.edu        %(class_name)s(ExtMachInst machInst);
1822124SN/A
1832124SN/A        %(BasicExecDeclare)s
1842124SN/A
1852124SN/A        %(InitiateAccDeclare)s
1862124SN/A
1872124SN/A        %(CompleteAccDeclare)s
1884661Sksewell@umich.edu
1894661Sksewell@umich.edu        %(MemAccSizeDeclare)s
1902124SN/A    };
1912022SN/A}};
1922022SN/A
1932124SN/A
1942124SN/Adef template InitiateAccDeclare {{
1952132SN/A    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
1962022SN/A}};
1972124SN/A
1982124SN/A
1992124SN/Adef template CompleteAccDeclare {{
2004661Sksewell@umich.edu    Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
2012124SN/A}};
2022124SN/A
2034661Sksewell@umich.edudef template MemAccSizeDeclare {{
2044661Sksewell@umich.edu    int memAccSize(%(CPU_exec_context)s *xc);
2054661Sksewell@umich.edu}};
2062124SN/A
2073953Sstever@eecs.umich.edudef template EACompConstructor {{
2082124SN/A    /** TODO: change op_class to AddrGenOp or something (requires
2092124SN/A     * creating new member of OpClass enum in op_class.hh, updating
2102124SN/A     * config files, etc.). */
2114661Sksewell@umich.edu    inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
2122124SN/A        : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
2132124SN/A    {
2143953Sstever@eecs.umich.edu        %(constructor)s;
2152124SN/A    }
2163953Sstever@eecs.umich.edu}};
2172124SN/A
2183953Sstever@eecs.umich.edu
2193953Sstever@eecs.umich.edudef template MemAccConstructor {{
2204661Sksewell@umich.edu    inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
2212124SN/A        : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
2222124SN/A    {
2233953Sstever@eecs.umich.edu        %(constructor)s;
2242124SN/A    }
2253953Sstever@eecs.umich.edu}};
2262124SN/A
2273953Sstever@eecs.umich.edu
2283953Sstever@eecs.umich.edudef template LoadStoreConstructor {{
2294661Sksewell@umich.edu    inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
2302124SN/A         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
2312124SN/A                          new EAComp(machInst), new MemAcc(machInst))
2322124SN/A    {
2332124SN/A        %(constructor)s;
2342124SN/A    }
2352124SN/A}};
2362124SN/A
2372124SN/A
2382124SN/Adef template EACompExecute {{
2392132SN/A    Fault
2402124SN/A    %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
2412124SN/A                                   Trace::InstRecord *traceData) const
2422124SN/A    {
2432124SN/A        Addr EA;
2442132SN/A        Fault fault = NoFault;
2452124SN/A
2462124SN/A        %(fp_enable_check)s;
2472124SN/A        %(op_decl)s;
2482124SN/A        %(op_rd)s;
2493953Sstever@eecs.umich.edu        %(ea_code)s;
2502124SN/A
2514661Sksewell@umich.edu        // NOTE: Trace Data is written using execute or completeAcc templates
2522124SN/A        if (fault == NoFault) {
2532124SN/A            xc->setEA(EA);
2542124SN/A        }
2552124SN/A
2562124SN/A        return fault;
2572124SN/A    }
2582124SN/A}};
2592124SN/A
2602124SN/Adef template LoadMemAccExecute {{
2612132SN/A    Fault
2622124SN/A    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
2632124SN/A                                   Trace::InstRecord *traceData) const
2642124SN/A    {
2652239SN/A        Addr EA;
2662132SN/A        Fault fault = NoFault;
2672239SN/A
2682239SN/A        %(op_decl)s;
2692239SN/A        %(op_rd)s;
2704661Sksewell@umich.edu
2712239SN/A        EA = xc->getEA();
2722239SN/A
2734661Sksewell@umich.edu        fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
2742239SN/A
2754661Sksewell@umich.edu        %(memacc_code)s;
2764661Sksewell@umich.edu
2774661Sksewell@umich.edu        // NOTE: Write back data using execute or completeAcc templates
2782239SN/A
2792124SN/A        return fault;
2802124SN/A    }
2812124SN/A}};
2822124SN/A
2832124SN/A
2842124SN/Adef template LoadExecute {{
2852132SN/A    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
2862124SN/A                                  Trace::InstRecord *traceData) const
2872124SN/A    {
2882124SN/A        Addr EA;
2892132SN/A        Fault fault = NoFault;
2902124SN/A
2912124SN/A        %(fp_enable_check)s;
2922124SN/A        %(op_decl)s;
2932124SN/A        %(op_rd)s;
2942124SN/A        %(ea_code)s;
2952124SN/A
2962124SN/A        if (fault == NoFault) {
2972124SN/A            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
2982124SN/A            %(memacc_code)s;
2992124SN/A        }
3002124SN/A
3012124SN/A        if (fault == NoFault) {
3022124SN/A            %(op_wb)s;
3032124SN/A        }
3042124SN/A
3052124SN/A        return fault;
3062124SN/A    }
3072124SN/A}};
3082124SN/A
3092124SN/A
3102124SN/Adef template LoadInitiateAcc {{
3112132SN/A    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
3122124SN/A                                      Trace::InstRecord *traceData) const
3132124SN/A    {
3142239SN/A        Addr EA;
3152132SN/A        Fault fault = NoFault;
3162239SN/A
3172239SN/A        %(fp_enable_check)s;
3182239SN/A        %(op_src_decl)s;
3192239SN/A        %(op_rd)s;
3202239SN/A        %(ea_code)s;
3212239SN/A
3222239SN/A        if (fault == NoFault) {
3232239SN/A            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
3242239SN/A        }
3252239SN/A
3262124SN/A        return fault;
3272124SN/A    }
3282124SN/A}};
3292124SN/A
3302124SN/Adef template LoadCompleteAcc {{
3314661Sksewell@umich.edu    Fault %(class_name)s::completeAcc(Packet *pkt,
3322124SN/A                                      %(CPU_exec_context)s *xc,
3332124SN/A                                      Trace::InstRecord *traceData) const
3342124SN/A    {
3352132SN/A        Fault fault = NoFault;
3362239SN/A
3372239SN/A        %(fp_enable_check)s;
3382506SN/A        %(op_decl)s;
3394661Sksewell@umich.edu        %(op_rd)s;
3402239SN/A
3412935Sksewell@umich.edu        Mem = pkt->get<typeof(Mem)>();
3422239SN/A
3432239SN/A        if (fault == NoFault) {
3442239SN/A            %(memacc_code)s;
3452239SN/A        }
3462239SN/A
3472239SN/A        if (fault == NoFault) {
3482239SN/A            %(op_wb)s;
3492239SN/A        }
3502239SN/A
3512124SN/A        return fault;
3522124SN/A    }
3532124SN/A}};
3542124SN/A
3552124SN/A
3564661Sksewell@umich.edu
3574661Sksewell@umich.edudef template LoadStoreMemAccSize {{
3584661Sksewell@umich.edu    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
3594661Sksewell@umich.edu    {
3604661Sksewell@umich.edu        // Return the memory access size in bytes
3614661Sksewell@umich.edu        return (%(mem_acc_size)d / 8);
3624661Sksewell@umich.edu    }
3634661Sksewell@umich.edu}};
3644661Sksewell@umich.edu
3652124SN/Adef template StoreMemAccExecute {{
3662132SN/A    Fault
3672124SN/A    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
3682124SN/A                                   Trace::InstRecord *traceData) const
3692124SN/A    {
3702239SN/A        Addr EA;
3712132SN/A        Fault fault = NoFault;
3724056Sstever@eecs.umich.edu
3734056Sstever@eecs.umich.edu        %(fp_enable_check)s;
3744056Sstever@eecs.umich.edu        %(op_decl)s;
3754056Sstever@eecs.umich.edu        %(op_rd)s;
3764661Sksewell@umich.edu
3774056Sstever@eecs.umich.edu        EA = xc->getEA();
3784056Sstever@eecs.umich.edu
3794056Sstever@eecs.umich.edu        if (fault == NoFault) {
3804056Sstever@eecs.umich.edu            %(memacc_code)s;
3814056Sstever@eecs.umich.edu        }
3824056Sstever@eecs.umich.edu
3834056Sstever@eecs.umich.edu        if (fault == NoFault) {
3844056Sstever@eecs.umich.edu            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
3854675Sksewell@umich.edu                              memAccessFlags, NULL);
3864661Sksewell@umich.edu            // @NOTE: Need to Call Complete Access to Set Trace Data
3874661Sksewell@umich.edu            //if (traceData) { traceData->setData(Mem); }
3884056Sstever@eecs.umich.edu        }
3894056Sstever@eecs.umich.edu
3904056Sstever@eecs.umich.edu        return fault;
3914056Sstever@eecs.umich.edu    }
3924056Sstever@eecs.umich.edu}};
3934056Sstever@eecs.umich.edu
3944056Sstever@eecs.umich.edudef template StoreCondMemAccExecute {{
3954056Sstever@eecs.umich.edu    Fault
3964056Sstever@eecs.umich.edu    %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
3974056Sstever@eecs.umich.edu                                   Trace::InstRecord *traceData) const
3984056Sstever@eecs.umich.edu    {
3994056Sstever@eecs.umich.edu        Addr EA;
4004056Sstever@eecs.umich.edu        Fault fault = NoFault;
4012239SN/A        uint64_t write_result = 0;
4022239SN/A
4032239SN/A        %(fp_enable_check)s;
4042239SN/A        %(op_decl)s;
4052239SN/A        %(op_rd)s;
4062239SN/A        EA = xc->getEA();
4072239SN/A
4082239SN/A        if (fault == NoFault) {
4093953Sstever@eecs.umich.edu            %(memacc_code)s;
4102239SN/A        }
4112239SN/A
4122239SN/A        if (fault == NoFault) {
4132239SN/A            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
4142239SN/A                              memAccessFlags, &write_result);
4152239SN/A            if (traceData) { traceData->setData(Mem); }
4162239SN/A        }
4172239SN/A
4182239SN/A        if (fault == NoFault) {
4192239SN/A            %(postacc_code)s;
4202239SN/A        }
4212239SN/A
4222239SN/A        if (fault == NoFault) {
4232239SN/A            %(op_wb)s;
4242239SN/A        }
4252239SN/A
4262124SN/A        return fault;
4272124SN/A    }
4282124SN/A}};
4292124SN/A
4302124SN/Adef template StoreExecute {{
4312132SN/A    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
4322124SN/A                                  Trace::InstRecord *traceData) const
4332124SN/A    {
4342124SN/A        Addr EA;
4352132SN/A        Fault fault = NoFault;
4364056Sstever@eecs.umich.edu
4374056Sstever@eecs.umich.edu        %(fp_enable_check)s;
4384056Sstever@eecs.umich.edu        %(op_decl)s;
4394056Sstever@eecs.umich.edu        %(op_rd)s;
4404056Sstever@eecs.umich.edu        %(ea_code)s;
4414056Sstever@eecs.umich.edu
4424056Sstever@eecs.umich.edu        if (fault == NoFault) {
4434056Sstever@eecs.umich.edu            %(memacc_code)s;
4444056Sstever@eecs.umich.edu        }
4454056Sstever@eecs.umich.edu
4464056Sstever@eecs.umich.edu        if (fault == NoFault) {
4474056Sstever@eecs.umich.edu            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
4484675Sksewell@umich.edu                              memAccessFlags, NULL);
4494056Sstever@eecs.umich.edu            if (traceData) { traceData->setData(Mem); }
4504056Sstever@eecs.umich.edu        }
4514056Sstever@eecs.umich.edu
4524056Sstever@eecs.umich.edu        if (fault == NoFault) {
4534056Sstever@eecs.umich.edu            %(postacc_code)s;
4544056Sstever@eecs.umich.edu        }
4554056Sstever@eecs.umich.edu
4564056Sstever@eecs.umich.edu        if (fault == NoFault) {
4574056Sstever@eecs.umich.edu            %(op_wb)s;
4584056Sstever@eecs.umich.edu        }
4594056Sstever@eecs.umich.edu
4604056Sstever@eecs.umich.edu        return fault;
4614056Sstever@eecs.umich.edu    }
4624056Sstever@eecs.umich.edu}};
4634056Sstever@eecs.umich.edu
4644056Sstever@eecs.umich.edudef template StoreCondExecute {{
4654056Sstever@eecs.umich.edu    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
4664056Sstever@eecs.umich.edu                                  Trace::InstRecord *traceData) const
4674056Sstever@eecs.umich.edu    {
4684056Sstever@eecs.umich.edu        Addr EA;
4694056Sstever@eecs.umich.edu        Fault fault = NoFault;
4702124SN/A        uint64_t write_result = 0;
4712124SN/A
4722124SN/A        %(fp_enable_check)s;
4732124SN/A        %(op_decl)s;
4742124SN/A        %(op_rd)s;
4752124SN/A        %(ea_code)s;
4762124SN/A
4772124SN/A        if (fault == NoFault) {
4782124SN/A            %(memacc_code)s;
4792124SN/A        }
4802124SN/A
4812124SN/A        if (fault == NoFault) {
4822124SN/A            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
4832124SN/A                              memAccessFlags, &write_result);
4842124SN/A            if (traceData) { traceData->setData(Mem); }
4852124SN/A        }
4862124SN/A
4872124SN/A        if (fault == NoFault) {
4882124SN/A            %(postacc_code)s;
4892124SN/A        }
4902124SN/A
4912124SN/A        if (fault == NoFault) {
4922124SN/A            %(op_wb)s;
4932124SN/A        }
4942124SN/A
4952124SN/A        return fault;
4962124SN/A    }
4972124SN/A}};
4982124SN/A
4992124SN/Adef template StoreInitiateAcc {{
5002132SN/A    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
5012124SN/A                                      Trace::InstRecord *traceData) const
5022124SN/A    {
5032239SN/A        Addr EA;
5042132SN/A        Fault fault = NoFault;
5052239SN/A
5062239SN/A        %(fp_enable_check)s;
5072506SN/A        %(op_decl)s;
5082239SN/A        %(op_rd)s;
5092239SN/A        %(ea_code)s;
5102239SN/A
5112239SN/A        if (fault == NoFault) {
5122239SN/A            %(memacc_code)s;
5132239SN/A        }
5142239SN/A
5152239SN/A        if (fault == NoFault) {
5162239SN/A            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
5172935Sksewell@umich.edu                              memAccessFlags, NULL);
5182239SN/A            if (traceData) { traceData->setData(Mem); }
5192239SN/A        }
5202239SN/A
5212124SN/A        return fault;
5222124SN/A    }
5232124SN/A}};
5242124SN/A
5252124SN/A
5262124SN/Adef template StoreCompleteAcc {{
5274661Sksewell@umich.edu    Fault %(class_name)s::completeAcc(Packet *pkt,
5282124SN/A                                      %(CPU_exec_context)s *xc,
5292124SN/A                                      Trace::InstRecord *traceData) const
5302124SN/A    {
5312132SN/A        Fault fault = NoFault;
5322239SN/A
5332239SN/A        %(fp_enable_check)s;
5342239SN/A        %(op_dest_decl)s;
5352239SN/A
5362935Sksewell@umich.edu        if (fault == NoFault) {
5372935Sksewell@umich.edu            %(postacc_code)s;
5382935Sksewell@umich.edu        }
5392935Sksewell@umich.edu
5402935Sksewell@umich.edu        if (fault == NoFault) {
5412935Sksewell@umich.edu            %(op_wb)s;
5424661Sksewell@umich.edu
5434673Sksewell@umich.edu            if (traceData) { traceData->setData(getStoreData(xc, pkt)); }
5442935Sksewell@umich.edu        }
5452935Sksewell@umich.edu
5462935Sksewell@umich.edu        return fault;
5472935Sksewell@umich.edu    }
5482935Sksewell@umich.edu}};
5492935Sksewell@umich.edu
5502935Sksewell@umich.edudef template StoreCondCompleteAcc {{
5514661Sksewell@umich.edu    Fault %(class_name)s::completeAcc(Packet *pkt,
5522935Sksewell@umich.edu                                      %(CPU_exec_context)s *xc,
5532935Sksewell@umich.edu                                      Trace::InstRecord *traceData) const
5542935Sksewell@umich.edu    {
5552935Sksewell@umich.edu        Fault fault = NoFault;
5562935Sksewell@umich.edu
5572935Sksewell@umich.edu        %(fp_enable_check)s;
5582935Sksewell@umich.edu        %(op_dest_decl)s;
5592935Sksewell@umich.edu
5604055Ssaidi@eecs.umich.edu        uint64_t write_result = pkt->req->getExtraData();
5612239SN/A
5622239SN/A        if (fault == NoFault) {
5632239SN/A            %(postacc_code)s;
5642239SN/A        }
5652239SN/A
5662239SN/A        if (fault == NoFault) {
5672239SN/A            %(op_wb)s;
5682239SN/A        }
5692239SN/A
5702124SN/A        return fault;
5712124SN/A    }
5722124SN/A}};
5732124SN/A
5742686Sksewell@umich.edu
5752686Sksewell@umich.edudef template MiscMemAccExecute {{
5762686Sksewell@umich.edu    Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
5772686Sksewell@umich.edu                                          Trace::InstRecord *traceData) const
5782686Sksewell@umich.edu    {
5792686Sksewell@umich.edu        Addr EA;
5802686Sksewell@umich.edu        Fault fault = NoFault;
5812686Sksewell@umich.edu
5822686Sksewell@umich.edu        %(fp_enable_check)s;
5832686Sksewell@umich.edu        %(op_decl)s;
5842686Sksewell@umich.edu        %(op_rd)s;
5852686Sksewell@umich.edu        EA = xc->getEA();
5862686Sksewell@umich.edu
5872686Sksewell@umich.edu        if (fault == NoFault) {
5883953Sstever@eecs.umich.edu            %(memacc_code)s;
5892686Sksewell@umich.edu        }
5902686Sksewell@umich.edu
5912686Sksewell@umich.edu        return NoFault;
5922686Sksewell@umich.edu    }
5932686Sksewell@umich.edu}};
5942686Sksewell@umich.edu
5952686Sksewell@umich.edudef template MiscExecute {{
5962686Sksewell@umich.edu    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
5972686Sksewell@umich.edu                                  Trace::InstRecord *traceData) const
5982686Sksewell@umich.edu    {
5992686Sksewell@umich.edu        Addr EA;
6002686Sksewell@umich.edu        Fault fault = NoFault;
6012686Sksewell@umich.edu
6022686Sksewell@umich.edu        %(fp_enable_check)s;
6032686Sksewell@umich.edu        %(op_decl)s;
6042686Sksewell@umich.edu        %(op_rd)s;
6052686Sksewell@umich.edu        %(ea_code)s;
6062686Sksewell@umich.edu
6072686Sksewell@umich.edu        if (fault == NoFault) {
6082686Sksewell@umich.edu            %(memacc_code)s;
6092686Sksewell@umich.edu        }
6102686Sksewell@umich.edu
6112686Sksewell@umich.edu        return NoFault;
6122686Sksewell@umich.edu    }
6132686Sksewell@umich.edu}};
6142686Sksewell@umich.edu
6152686Sksewell@umich.edudef template MiscInitiateAcc {{
6162686Sksewell@umich.edu    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
6172686Sksewell@umich.edu                                      Trace::InstRecord *traceData) const
6182686Sksewell@umich.edu    {
6192686Sksewell@umich.edu        panic("Misc instruction does not support split access method!");
6202686Sksewell@umich.edu        return NoFault;
6212686Sksewell@umich.edu    }
6222686Sksewell@umich.edu}};
6232686Sksewell@umich.edu
6242686Sksewell@umich.edu
6252686Sksewell@umich.edudef template MiscCompleteAcc {{
6264661Sksewell@umich.edu    Fault %(class_name)s::completeAcc(Packet *pkt,
6272686Sksewell@umich.edu                                      %(CPU_exec_context)s *xc,
6282686Sksewell@umich.edu                                      Trace::InstRecord *traceData) const
6292686Sksewell@umich.edu    {
6302686Sksewell@umich.edu        panic("Misc instruction does not support split access method!");
6312686Sksewell@umich.edu
6322686Sksewell@umich.edu        return NoFault;
6332686Sksewell@umich.edu    }
6342686Sksewell@umich.edu}};
6352686Sksewell@umich.edu
6364661Sksewell@umich.edu
6374661Sksewell@umich.edudef template MiscMemAccSize {{
6384661Sksewell@umich.edu    int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
6394661Sksewell@umich.edu    {
6404661Sksewell@umich.edu        panic("Misc instruction does not support split access method!");
6414661Sksewell@umich.edu        return 0;
6424661Sksewell@umich.edu    }
6434661Sksewell@umich.edu}};
6444661Sksewell@umich.edu
6452124SN/Adef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
6462124SN/A                     mem_flags = [], inst_flags = []) {{
6472124SN/A    (header_output, decoder_output, decode_block, exec_output) = \
6482124SN/A        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
6492750Sksewell@umich.edu                      decode_template = ImmNopCheckDecode,
6502124SN/A                      exec_template_base = 'Load')
6512124SN/A}};
6522124SN/A
6532124SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
6542124SN/A                     mem_flags = [], inst_flags = []) {{
6552124SN/A    (header_output, decoder_output, decode_block, exec_output) = \
6562124SN/A        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
6572124SN/A                      exec_template_base = 'Store')
6582124SN/A}};
6592124SN/A
6602686Sksewell@umich.edudef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
6612573SN/A                     mem_flags = [], inst_flags = []) {{
6622573SN/A    (header_output, decoder_output, decode_block, exec_output) = \
6632573SN/A        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
6642750Sksewell@umich.edu                      decode_template = ImmNopCheckDecode,
6652573SN/A                      exec_template_base = 'Load')
6662573SN/A}};
6672573SN/A
6682686Sksewell@umich.edudef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
6692573SN/A                     mem_flags = [], inst_flags = []) {{
6702573SN/A    (header_output, decoder_output, decode_block, exec_output) = \
6712573SN/A        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
6722573SN/A                      exec_template_base = 'Store')
6732573SN/A}};
6742573SN/A
6752686Sksewell@umich.edudef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
6762686Sksewell@umich.edu                     mem_flags = [], inst_flags = []) {{
6772686Sksewell@umich.edu    decl_code = 'uint32_t mem_word = Mem.uw;\n'
6782686Sksewell@umich.edu    decl_code += 'uint32_t unalign_addr = Rs + disp;\n'
6792686Sksewell@umich.edu    decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n'
6802686Sksewell@umich.edu    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
6812686Sksewell@umich.edu    decl_code += '\tbyte_offset ^= 3;\n'
6822686Sksewell@umich.edu    decl_code += '#endif\n'
6832573SN/A
6842686Sksewell@umich.edu    memacc_code = decl_code + memacc_code
6852686Sksewell@umich.edu
6862686Sksewell@umich.edu    (header_output, decoder_output, decode_block, exec_output) = \
6872686Sksewell@umich.edu        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
6882750Sksewell@umich.edu                      decode_template = ImmNopCheckDecode,
6892686Sksewell@umich.edu                      exec_template_base = 'Load')
6902686Sksewell@umich.edu}};
6912686Sksewell@umich.edu
6922686Sksewell@umich.edudef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
6932686Sksewell@umich.edu                     mem_flags = [], inst_flags = []) {{
6942686Sksewell@umich.edu    decl_code = 'uint32_t mem_word = 0;\n'
6952686Sksewell@umich.edu    decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
6962686Sksewell@umich.edu    decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
6972686Sksewell@umich.edu    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
6982686Sksewell@umich.edu    decl_code += '\tbyte_offset ^= 3;\n'
6992686Sksewell@umich.edu    decl_code += '#endif\n'
7002686Sksewell@umich.edu    decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
7014661Sksewell@umich.edu    #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);'
7022686Sksewell@umich.edu    memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
7032686Sksewell@umich.edu
7042686Sksewell@umich.edu    (header_output, decoder_output, decode_block, exec_output) = \
7052686Sksewell@umich.edu        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
7062686Sksewell@umich.edu                      exec_template_base = 'Store')
7072686Sksewell@umich.edu}};
7082686Sksewell@umich.edu
7092686Sksewell@umich.edudef format Prefetch(ea_code = {{ EA = Rs + disp; }},
7102686Sksewell@umich.edu                          mem_flags = [], pf_flags = [], inst_flags = []) {{
7112686Sksewell@umich.edu    pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
7122686Sksewell@umich.edu    pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
7132686Sksewell@umich.edu                                  'IsDataPrefetch', 'MemReadOp']
7142686Sksewell@umich.edu
7152686Sksewell@umich.edu    (header_output, decoder_output, decode_block, exec_output) = \
7162686Sksewell@umich.edu        LoadStoreBase(name, Name, ea_code,
7172686Sksewell@umich.edu                      'xc->prefetch(EA, memAccessFlags);',
7182686Sksewell@umich.edu                      pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
7192686Sksewell@umich.edu
7202686Sksewell@umich.edu}};
7212686Sksewell@umich.edu
7222686Sksewell@umich.edudef format StoreCond(memacc_code, postacc_code,
7232686Sksewell@umich.edu                     ea_code = {{ EA = Rs + disp; }},
7242495SN/A                     mem_flags = [], inst_flags = []) {{
7252495SN/A    (header_output, decoder_output, decode_block, exec_output) = \
7262495SN/A        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
7272935Sksewell@umich.edu                      postacc_code, exec_template_base = 'StoreCond')
7282495SN/A}};
729