mem.isa revision 2754
12124SN/A// -*- mode:c++ -*- 22124SN/A 32754Sksewell@umich.edu// Copyright (c) 2006 The Regents of The University of Michigan 42124SN/A// All rights reserved. 52022SN/A// 62124SN/A// Redistribution and use in source and binary forms, with or without 72124SN/A// modification, are permitted provided that the following conditions are 82124SN/A// met: redistributions of source code must retain the above copyright 92124SN/A// notice, this list of conditions and the following disclaimer; 102124SN/A// redistributions in binary form must reproduce the above copyright 112124SN/A// notice, this list of conditions and the following disclaimer in the 122124SN/A// documentation and/or other materials provided with the distribution; 132124SN/A// neither the name of the copyright holders nor the names of its 142124SN/A// contributors may be used to endorse or promote products derived from 152124SN/A// this software without specific prior written permission. 162022SN/A// 172124SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182124SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192124SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202124SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212124SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222124SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232124SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242124SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252124SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262124SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272124SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Gabe Black 302665Ssaidi@eecs.umich.edu// Korey Sewell 312022SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342706Sksewell@umich.edu// Memory-format instructions 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372022SN/Aoutput header {{ 382124SN/A /** 392124SN/A * Base class for general Mips memory-format instructions. 402124SN/A */ 412124SN/A class Memory : public MipsStaticInst 422124SN/A { 432124SN/A protected: 442124SN/A 452124SN/A /// Memory request flags. See mem_req_base.hh. 462124SN/A unsigned memAccessFlags; 472124SN/A /// Pointer to EAComp object. 482124SN/A const StaticInstPtr eaCompPtr; 492124SN/A /// Pointer to MemAcc object. 502124SN/A const StaticInstPtr memAccPtr; 512239SN/A 522124SN/A /// Displacement for EA calculation (signed). 532124SN/A int32_t disp; 542124SN/A 552124SN/A /// Constructor 562124SN/A Memory(const char *mnem, MachInst _machInst, OpClass __opClass, 572124SN/A StaticInstPtr _eaCompPtr = nullStaticInstPtr, 582124SN/A StaticInstPtr _memAccPtr = nullStaticInstPtr) 592124SN/A : MipsStaticInst(mnem, _machInst, __opClass), 602124SN/A memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), 612742Sksewell@umich.edu disp(sext<16>(OFFSET)) 622022SN/A { 632124SN/A } 642022SN/A 652124SN/A std::string 662124SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 672022SN/A 682124SN/A public: 692124SN/A 702124SN/A const StaticInstPtr &eaCompInst() const { return eaCompPtr; } 712124SN/A const StaticInstPtr &memAccInst() const { return memAccPtr; } 722124SN/A }; 732124SN/A 742742Sksewell@umich.edu /** 752742Sksewell@umich.edu * Base class for a few miscellaneous memory-format insts 762742Sksewell@umich.edu * that don't interpret the disp field 772742Sksewell@umich.edu */ 782742Sksewell@umich.edu class MemoryNoDisp : public Memory 792742Sksewell@umich.edu { 802742Sksewell@umich.edu protected: 812742Sksewell@umich.edu /// Constructor 822742Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 832742Sksewell@umich.edu StaticInstPtr _eaCompPtr = nullStaticInstPtr, 842742Sksewell@umich.edu StaticInstPtr _memAccPtr = nullStaticInstPtr) 852742Sksewell@umich.edu : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr) 862742Sksewell@umich.edu { 872742Sksewell@umich.edu } 882742Sksewell@umich.edu 892742Sksewell@umich.edu std::string 902742Sksewell@umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 912742Sksewell@umich.edu }; 922022SN/A}}; 932022SN/A 942124SN/A 952022SN/Aoutput decoder {{ 962124SN/A std::string 972124SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 982124SN/A { 992742Sksewell@umich.edu return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 1002239SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 1012124SN/A } 1022124SN/A 1032742Sksewell@umich.edu std::string 1042742Sksewell@umich.edu MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1052742Sksewell@umich.edu { 1062742Sksewell@umich.edu return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 1072742Sksewell@umich.edu flags[IsFloating] ? 'f' : 'r', 1082742Sksewell@umich.edu flags[IsFloating] ? FD : RD, 1092742Sksewell@umich.edu RS, RT); 1102742Sksewell@umich.edu } 1112022SN/A}}; 1122022SN/A 1132124SN/Adef template LoadStoreDeclare {{ 1142124SN/A /** 1152124SN/A * Static instruction class for "%(mnemonic)s". 1162124SN/A */ 1172124SN/A class %(class_name)s : public %(base_class)s 1182124SN/A { 1192124SN/A protected: 1202124SN/A 1212124SN/A /** 1222124SN/A * "Fake" effective address computation class for "%(mnemonic)s". 1232124SN/A */ 1242124SN/A class EAComp : public %(base_class)s 1252124SN/A { 1262124SN/A public: 1272124SN/A /// Constructor 1282124SN/A EAComp(MachInst machInst); 1292124SN/A 1302124SN/A %(BasicExecDeclare)s 1312124SN/A }; 1322124SN/A 1332124SN/A /** 1342124SN/A * "Fake" memory access instruction class for "%(mnemonic)s". 1352124SN/A */ 1362124SN/A class MemAcc : public %(base_class)s 1372124SN/A { 1382124SN/A public: 1392124SN/A /// Constructor 1402124SN/A MemAcc(MachInst machInst); 1412124SN/A 1422124SN/A %(BasicExecDeclare)s 1432124SN/A }; 1442124SN/A 1452124SN/A public: 1462124SN/A 1472124SN/A /// Constructor. 1482124SN/A %(class_name)s(MachInst machInst); 1492124SN/A 1502124SN/A %(BasicExecDeclare)s 1512124SN/A 1522124SN/A %(InitiateAccDeclare)s 1532124SN/A 1542124SN/A %(CompleteAccDeclare)s 1552124SN/A }; 1562022SN/A}}; 1572022SN/A 1582124SN/A 1592124SN/Adef template InitiateAccDeclare {{ 1602132SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1612022SN/A}}; 1622124SN/A 1632124SN/A 1642124SN/Adef template CompleteAccDeclare {{ 1652132SN/A Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1662124SN/A}}; 1672124SN/A 1682124SN/A 1692124SN/Adef template LoadStoreConstructor {{ 1702124SN/A /** TODO: change op_class to AddrGenOp or something (requires 1712124SN/A * creating new member of OpClass enum in op_class.hh, updating 1722124SN/A * config files, etc.). */ 1732124SN/A inline %(class_name)s::EAComp::EAComp(MachInst machInst) 1742124SN/A : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) 1752124SN/A { 1762124SN/A %(ea_constructor)s; 1772124SN/A } 1782124SN/A 1792124SN/A inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) 1802124SN/A : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) 1812124SN/A { 1822124SN/A %(memacc_constructor)s; 1832124SN/A } 1842124SN/A 1852124SN/A inline %(class_name)s::%(class_name)s(MachInst machInst) 1862124SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1872124SN/A new EAComp(machInst), new MemAcc(machInst)) 1882124SN/A { 1892124SN/A %(constructor)s; 1902124SN/A } 1912124SN/A}}; 1922124SN/A 1932124SN/A 1942124SN/Adef template EACompExecute {{ 1952132SN/A Fault 1962124SN/A %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, 1972124SN/A Trace::InstRecord *traceData) const 1982124SN/A { 1992124SN/A Addr EA; 2002132SN/A Fault fault = NoFault; 2012124SN/A 2022124SN/A %(fp_enable_check)s; 2032124SN/A %(op_decl)s; 2042124SN/A %(op_rd)s; 2052124SN/A %(code)s; 2062124SN/A 2072124SN/A if (fault == NoFault) { 2082124SN/A %(op_wb)s; 2092124SN/A xc->setEA(EA); 2102124SN/A } 2112124SN/A 2122124SN/A return fault; 2132124SN/A } 2142124SN/A}}; 2152124SN/A 2162124SN/Adef template LoadMemAccExecute {{ 2172132SN/A Fault 2182124SN/A %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 2192124SN/A Trace::InstRecord *traceData) const 2202124SN/A { 2212239SN/A Addr EA; 2222132SN/A Fault fault = NoFault; 2232239SN/A 2242239SN/A %(fp_enable_check)s; 2252239SN/A %(op_decl)s; 2262239SN/A %(op_rd)s; 2272239SN/A EA = xc->getEA(); 2282239SN/A 2292239SN/A if (fault == NoFault) { 2302239SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 2312239SN/A %(code)s; 2322239SN/A } 2332239SN/A 2342239SN/A if (fault == NoFault) { 2352239SN/A %(op_wb)s; 2362239SN/A } 2372239SN/A 2382124SN/A return fault; 2392124SN/A } 2402124SN/A}}; 2412124SN/A 2422124SN/A 2432124SN/Adef template LoadExecute {{ 2442132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2452124SN/A Trace::InstRecord *traceData) const 2462124SN/A { 2472124SN/A Addr EA; 2482132SN/A Fault fault = NoFault; 2492124SN/A 2502124SN/A %(fp_enable_check)s; 2512124SN/A %(op_decl)s; 2522124SN/A %(op_rd)s; 2532124SN/A %(ea_code)s; 2542124SN/A 2552124SN/A if (fault == NoFault) { 2562124SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 2572124SN/A %(memacc_code)s; 2582124SN/A } 2592124SN/A 2602124SN/A if (fault == NoFault) { 2612124SN/A %(op_wb)s; 2622124SN/A } 2632124SN/A 2642124SN/A return fault; 2652124SN/A } 2662124SN/A}}; 2672124SN/A 2682124SN/A 2692124SN/Adef template LoadInitiateAcc {{ 2702132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2712124SN/A Trace::InstRecord *traceData) const 2722124SN/A { 2732239SN/A Addr EA; 2742132SN/A Fault fault = NoFault; 2752239SN/A 2762239SN/A %(fp_enable_check)s; 2772239SN/A %(op_src_decl)s; 2782239SN/A %(op_rd)s; 2792239SN/A %(ea_code)s; 2802239SN/A 2812239SN/A if (fault == NoFault) { 2822239SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 2832239SN/A } 2842239SN/A 2852124SN/A return fault; 2862124SN/A } 2872124SN/A}}; 2882124SN/A 2892124SN/A 2902124SN/Adef template LoadCompleteAcc {{ 2912132SN/A Fault %(class_name)s::completeAcc(uint8_t *data, 2922124SN/A %(CPU_exec_context)s *xc, 2932124SN/A Trace::InstRecord *traceData) const 2942124SN/A { 2952132SN/A Fault fault = NoFault; 2962239SN/A 2972239SN/A %(fp_enable_check)s; 2982506SN/A %(op_decl)s; 2992239SN/A 3002239SN/A memcpy(&Mem, data, sizeof(Mem)); 3012239SN/A 3022239SN/A if (fault == NoFault) { 3032239SN/A %(memacc_code)s; 3042239SN/A } 3052239SN/A 3062239SN/A if (fault == NoFault) { 3072239SN/A %(op_wb)s; 3082239SN/A } 3092239SN/A 3102124SN/A return fault; 3112124SN/A } 3122124SN/A}}; 3132124SN/A 3142124SN/A 3152124SN/Adef template StoreMemAccExecute {{ 3162132SN/A Fault 3172124SN/A %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 3182124SN/A Trace::InstRecord *traceData) const 3192124SN/A { 3202239SN/A Addr EA; 3212132SN/A Fault fault = NoFault; 3222239SN/A uint64_t write_result = 0; 3232239SN/A 3242239SN/A %(fp_enable_check)s; 3252239SN/A %(op_decl)s; 3262239SN/A %(op_rd)s; 3272239SN/A EA = xc->getEA(); 3282239SN/A 3292239SN/A if (fault == NoFault) { 3302239SN/A %(code)s; 3312239SN/A } 3322239SN/A 3332239SN/A if (fault == NoFault) { 3342239SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3352239SN/A memAccessFlags, &write_result); 3362239SN/A if (traceData) { traceData->setData(Mem); } 3372239SN/A } 3382239SN/A 3392239SN/A if (fault == NoFault) { 3402239SN/A %(postacc_code)s; 3412239SN/A } 3422239SN/A 3432239SN/A if (fault == NoFault) { 3442239SN/A %(op_wb)s; 3452239SN/A } 3462239SN/A 3472124SN/A return fault; 3482124SN/A } 3492124SN/A}}; 3502124SN/A 3512124SN/A 3522124SN/Adef template StoreExecute {{ 3532132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3542124SN/A Trace::InstRecord *traceData) const 3552124SN/A { 3562124SN/A Addr EA; 3572132SN/A Fault fault = NoFault; 3582124SN/A uint64_t write_result = 0; 3592124SN/A 3602124SN/A %(fp_enable_check)s; 3612124SN/A %(op_decl)s; 3622124SN/A %(op_rd)s; 3632124SN/A %(ea_code)s; 3642124SN/A 3652124SN/A if (fault == NoFault) { 3662124SN/A %(memacc_code)s; 3672124SN/A } 3682124SN/A 3692124SN/A if (fault == NoFault) { 3702124SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3712124SN/A memAccessFlags, &write_result); 3722124SN/A if (traceData) { traceData->setData(Mem); } 3732124SN/A } 3742124SN/A 3752124SN/A if (fault == NoFault) { 3762124SN/A %(postacc_code)s; 3772124SN/A } 3782124SN/A 3792124SN/A if (fault == NoFault) { 3802124SN/A %(op_wb)s; 3812124SN/A } 3822124SN/A 3832124SN/A return fault; 3842124SN/A } 3852124SN/A}}; 3862124SN/A 3872124SN/Adef template StoreInitiateAcc {{ 3882132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3892124SN/A Trace::InstRecord *traceData) const 3902124SN/A { 3912239SN/A Addr EA; 3922132SN/A Fault fault = NoFault; 3932239SN/A uint64_t write_result = 0; 3942239SN/A 3952239SN/A %(fp_enable_check)s; 3962506SN/A %(op_decl)s; 3972239SN/A %(op_rd)s; 3982239SN/A %(ea_code)s; 3992239SN/A 4002239SN/A if (fault == NoFault) { 4012239SN/A %(memacc_code)s; 4022239SN/A } 4032239SN/A 4042239SN/A if (fault == NoFault) { 4052239SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 4062239SN/A memAccessFlags, &write_result); 4072239SN/A if (traceData) { traceData->setData(Mem); } 4082239SN/A } 4092239SN/A 4102124SN/A return fault; 4112124SN/A } 4122124SN/A}}; 4132124SN/A 4142124SN/A 4152124SN/Adef template StoreCompleteAcc {{ 4162132SN/A Fault %(class_name)s::completeAcc(uint8_t *data, 4172124SN/A %(CPU_exec_context)s *xc, 4182124SN/A Trace::InstRecord *traceData) const 4192124SN/A { 4202132SN/A Fault fault = NoFault; 4212239SN/A uint64_t write_result = 0; 4222239SN/A 4232239SN/A %(fp_enable_check)s; 4242239SN/A %(op_dest_decl)s; 4252239SN/A 4262239SN/A memcpy(&write_result, data, sizeof(write_result)); 4272239SN/A 4282239SN/A if (fault == NoFault) { 4292239SN/A %(postacc_code)s; 4302239SN/A } 4312239SN/A 4322239SN/A if (fault == NoFault) { 4332239SN/A %(op_wb)s; 4342239SN/A } 4352239SN/A 4362124SN/A return fault; 4372124SN/A } 4382124SN/A}}; 4392124SN/A 4402686Sksewell@umich.edu 4412686Sksewell@umich.edudef template MiscMemAccExecute {{ 4422686Sksewell@umich.edu Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 4432686Sksewell@umich.edu Trace::InstRecord *traceData) const 4442686Sksewell@umich.edu { 4452686Sksewell@umich.edu Addr EA; 4462686Sksewell@umich.edu Fault fault = NoFault; 4472686Sksewell@umich.edu 4482686Sksewell@umich.edu %(fp_enable_check)s; 4492686Sksewell@umich.edu %(op_decl)s; 4502686Sksewell@umich.edu %(op_rd)s; 4512686Sksewell@umich.edu EA = xc->getEA(); 4522686Sksewell@umich.edu 4532686Sksewell@umich.edu if (fault == NoFault) { 4542686Sksewell@umich.edu %(code)s; 4552686Sksewell@umich.edu } 4562686Sksewell@umich.edu 4572686Sksewell@umich.edu return NoFault; 4582686Sksewell@umich.edu } 4592686Sksewell@umich.edu}}; 4602686Sksewell@umich.edu 4612686Sksewell@umich.edudef template MiscExecute {{ 4622686Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 4632686Sksewell@umich.edu Trace::InstRecord *traceData) const 4642686Sksewell@umich.edu { 4652686Sksewell@umich.edu Addr EA; 4662686Sksewell@umich.edu Fault fault = NoFault; 4672686Sksewell@umich.edu 4682686Sksewell@umich.edu %(fp_enable_check)s; 4692686Sksewell@umich.edu %(op_decl)s; 4702686Sksewell@umich.edu %(op_rd)s; 4712686Sksewell@umich.edu %(ea_code)s; 4722686Sksewell@umich.edu 4732686Sksewell@umich.edu if (fault == NoFault) { 4742686Sksewell@umich.edu %(memacc_code)s; 4752686Sksewell@umich.edu } 4762686Sksewell@umich.edu 4772686Sksewell@umich.edu return NoFault; 4782686Sksewell@umich.edu } 4792686Sksewell@umich.edu}}; 4802686Sksewell@umich.edu 4812686Sksewell@umich.edudef template MiscInitiateAcc {{ 4822686Sksewell@umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4832686Sksewell@umich.edu Trace::InstRecord *traceData) const 4842686Sksewell@umich.edu { 4852686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4862686Sksewell@umich.edu return NoFault; 4872686Sksewell@umich.edu } 4882686Sksewell@umich.edu}}; 4892686Sksewell@umich.edu 4902686Sksewell@umich.edu 4912686Sksewell@umich.edudef template MiscCompleteAcc {{ 4922686Sksewell@umich.edu Fault %(class_name)s::completeAcc(uint8_t *data, 4932686Sksewell@umich.edu %(CPU_exec_context)s *xc, 4942686Sksewell@umich.edu Trace::InstRecord *traceData) const 4952686Sksewell@umich.edu { 4962686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4972686Sksewell@umich.edu 4982686Sksewell@umich.edu return NoFault; 4992686Sksewell@umich.edu } 5002686Sksewell@umich.edu}}; 5012686Sksewell@umich.edu 5022124SN/Adef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 5032124SN/A mem_flags = [], inst_flags = []) {{ 5042124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5052124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5062750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5072124SN/A exec_template_base = 'Load') 5082124SN/A}}; 5092124SN/A 5102124SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 5112124SN/A mem_flags = [], inst_flags = []) {{ 5122124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5132124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5142124SN/A exec_template_base = 'Store') 5152124SN/A}}; 5162124SN/A 5172686Sksewell@umich.edudef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5182573SN/A mem_flags = [], inst_flags = []) {{ 5192573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5202573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5212750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5222573SN/A exec_template_base = 'Load') 5232573SN/A}}; 5242573SN/A 5252686Sksewell@umich.edudef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5262573SN/A mem_flags = [], inst_flags = []) {{ 5272573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5282573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5292573SN/A exec_template_base = 'Store') 5302573SN/A}}; 5312573SN/A 5322686Sksewell@umich.edudef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5332686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5342686Sksewell@umich.edu decl_code = 'uint32_t mem_word = Mem.uw;\n' 5352686Sksewell@umich.edu decl_code += 'uint32_t unalign_addr = Rs + disp;\n' 5362686Sksewell@umich.edu decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n' 5372686Sksewell@umich.edu decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 5382686Sksewell@umich.edu decl_code += '\tbyte_offset ^= 3;\n' 5392686Sksewell@umich.edu decl_code += '#endif\n' 5402573SN/A 5412686Sksewell@umich.edu memacc_code = decl_code + memacc_code 5422686Sksewell@umich.edu 5432686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5442686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5452750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5462686Sksewell@umich.edu exec_template_base = 'Load') 5472686Sksewell@umich.edu}}; 5482686Sksewell@umich.edu 5492686Sksewell@umich.edudef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5502686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5512686Sksewell@umich.edu decl_code = 'uint32_t mem_word = 0;\n' 5522686Sksewell@umich.edu decl_code += 'uint32_t unaligned_addr = Rs + disp;\n' 5532686Sksewell@umich.edu decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n' 5542686Sksewell@umich.edu decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 5552686Sksewell@umich.edu decl_code += '\tbyte_offset ^= 3;\n' 5562686Sksewell@umich.edu decl_code += '#endif\n' 5572686Sksewell@umich.edu decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n' 5582686Sksewell@umich.edu memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 5592686Sksewell@umich.edu 5602686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5612686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5622686Sksewell@umich.edu exec_template_base = 'Store') 5632686Sksewell@umich.edu}}; 5642686Sksewell@umich.edu 5652686Sksewell@umich.edudef format Prefetch(ea_code = {{ EA = Rs + disp; }}, 5662686Sksewell@umich.edu mem_flags = [], pf_flags = [], inst_flags = []) {{ 5672686Sksewell@umich.edu pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT'] 5682686Sksewell@umich.edu pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 5692686Sksewell@umich.edu 'IsDataPrefetch', 'MemReadOp'] 5702686Sksewell@umich.edu 5712686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5722686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, 5732686Sksewell@umich.edu 'xc->prefetch(EA, memAccessFlags);', 5742686Sksewell@umich.edu pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5752686Sksewell@umich.edu 5762686Sksewell@umich.edu}}; 5772686Sksewell@umich.edu 5782686Sksewell@umich.edudef format StoreCond(memacc_code, postacc_code, 5792686Sksewell@umich.edu ea_code = {{ EA = Rs + disp; }}, 5802495SN/A mem_flags = [], inst_flags = []) {{ 5812495SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5822495SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5832495SN/A postacc_code, exec_template_base = 'Store') 5842495SN/A}}; 585