mem.isa revision 2706
12124SN/A// -*- mode:c++ -*- 22124SN/A 32124SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 42124SN/A// All rights reserved. 52022SN/A// 62124SN/A// Redistribution and use in source and binary forms, with or without 72124SN/A// modification, are permitted provided that the following conditions are 82124SN/A// met: redistributions of source code must retain the above copyright 92124SN/A// notice, this list of conditions and the following disclaimer; 102124SN/A// redistributions in binary form must reproduce the above copyright 112124SN/A// notice, this list of conditions and the following disclaimer in the 122124SN/A// documentation and/or other materials provided with the distribution; 132124SN/A// neither the name of the copyright holders nor the names of its 142124SN/A// contributors may be used to endorse or promote products derived from 152124SN/A// this software without specific prior written permission. 162022SN/A// 172124SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182124SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192124SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202124SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212124SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222124SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232124SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242124SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252124SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262124SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272124SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Gabe Black 302665Ssaidi@eecs.umich.edu// Korey Sewell 312022SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342706Sksewell@umich.edu// Memory-format instructions 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372022SN/Aoutput header {{ 382124SN/A /** 392124SN/A * Base class for general Mips memory-format instructions. 402124SN/A */ 412124SN/A class Memory : public MipsStaticInst 422124SN/A { 432124SN/A protected: 442124SN/A 452124SN/A /// Memory request flags. See mem_req_base.hh. 462124SN/A unsigned memAccessFlags; 472124SN/A /// Pointer to EAComp object. 482124SN/A const StaticInstPtr eaCompPtr; 492124SN/A /// Pointer to MemAcc object. 502124SN/A const StaticInstPtr memAccPtr; 512239SN/A 522124SN/A /// Displacement for EA calculation (signed). 532124SN/A int32_t disp; 542124SN/A 552124SN/A /// Constructor 562124SN/A Memory(const char *mnem, MachInst _machInst, OpClass __opClass, 572124SN/A StaticInstPtr _eaCompPtr = nullStaticInstPtr, 582124SN/A StaticInstPtr _memAccPtr = nullStaticInstPtr) 592124SN/A : MipsStaticInst(mnem, _machInst, __opClass), 602124SN/A memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), 612124SN/A disp(OFFSET) 622022SN/A { 632239SN/A //If Bit 15 is 1 then Sign Extend 642239SN/A int32_t temp = disp & 0x00008000; 652239SN/A 662239SN/A if (temp > 0) { 672239SN/A disp |= 0xFFFF0000; 682239SN/A } 692124SN/A } 702022SN/A 712124SN/A std::string 722124SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 732022SN/A 742124SN/A public: 752124SN/A 762124SN/A const StaticInstPtr &eaCompInst() const { return eaCompPtr; } 772124SN/A const StaticInstPtr &memAccInst() const { return memAccPtr; } 782124SN/A }; 792124SN/A 802022SN/A}}; 812022SN/A 822124SN/A 832022SN/Aoutput decoder {{ 842124SN/A std::string 852124SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 862124SN/A { 872124SN/A return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 882239SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 892124SN/A } 902124SN/A 912022SN/A}}; 922022SN/A 932124SN/Adef template LoadStoreDeclare {{ 942124SN/A /** 952124SN/A * Static instruction class for "%(mnemonic)s". 962124SN/A */ 972124SN/A class %(class_name)s : public %(base_class)s 982124SN/A { 992124SN/A protected: 1002124SN/A 1012124SN/A /** 1022124SN/A * "Fake" effective address computation class for "%(mnemonic)s". 1032124SN/A */ 1042124SN/A class EAComp : public %(base_class)s 1052124SN/A { 1062124SN/A public: 1072124SN/A /// Constructor 1082124SN/A EAComp(MachInst machInst); 1092124SN/A 1102124SN/A %(BasicExecDeclare)s 1112124SN/A }; 1122124SN/A 1132124SN/A /** 1142124SN/A * "Fake" memory access instruction class for "%(mnemonic)s". 1152124SN/A */ 1162124SN/A class MemAcc : public %(base_class)s 1172124SN/A { 1182124SN/A public: 1192124SN/A /// Constructor 1202124SN/A MemAcc(MachInst machInst); 1212124SN/A 1222124SN/A %(BasicExecDeclare)s 1232124SN/A }; 1242124SN/A 1252124SN/A public: 1262124SN/A 1272124SN/A /// Constructor. 1282124SN/A %(class_name)s(MachInst machInst); 1292124SN/A 1302124SN/A %(BasicExecDeclare)s 1312124SN/A 1322124SN/A %(InitiateAccDeclare)s 1332124SN/A 1342124SN/A %(CompleteAccDeclare)s 1352124SN/A }; 1362022SN/A}}; 1372022SN/A 1382124SN/A 1392124SN/Adef template InitiateAccDeclare {{ 1402132SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1412022SN/A}}; 1422124SN/A 1432124SN/A 1442124SN/Adef template CompleteAccDeclare {{ 1452132SN/A Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1462124SN/A}}; 1472124SN/A 1482124SN/A 1492124SN/Adef template LoadStoreConstructor {{ 1502124SN/A /** TODO: change op_class to AddrGenOp or something (requires 1512124SN/A * creating new member of OpClass enum in op_class.hh, updating 1522124SN/A * config files, etc.). */ 1532124SN/A inline %(class_name)s::EAComp::EAComp(MachInst machInst) 1542124SN/A : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) 1552124SN/A { 1562124SN/A %(ea_constructor)s; 1572124SN/A } 1582124SN/A 1592124SN/A inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) 1602124SN/A : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) 1612124SN/A { 1622124SN/A %(memacc_constructor)s; 1632124SN/A } 1642124SN/A 1652124SN/A inline %(class_name)s::%(class_name)s(MachInst machInst) 1662124SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1672124SN/A new EAComp(machInst), new MemAcc(machInst)) 1682124SN/A { 1692124SN/A %(constructor)s; 1702124SN/A } 1712124SN/A}}; 1722124SN/A 1732124SN/A 1742124SN/Adef template EACompExecute {{ 1752132SN/A Fault 1762124SN/A %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, 1772124SN/A Trace::InstRecord *traceData) const 1782124SN/A { 1792124SN/A Addr EA; 1802132SN/A Fault fault = NoFault; 1812124SN/A 1822124SN/A %(fp_enable_check)s; 1832124SN/A %(op_decl)s; 1842124SN/A %(op_rd)s; 1852124SN/A %(code)s; 1862124SN/A 1872124SN/A if (fault == NoFault) { 1882124SN/A %(op_wb)s; 1892124SN/A xc->setEA(EA); 1902124SN/A } 1912124SN/A 1922124SN/A return fault; 1932124SN/A } 1942124SN/A}}; 1952124SN/A 1962124SN/Adef template LoadMemAccExecute {{ 1972132SN/A Fault 1982124SN/A %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 1992124SN/A Trace::InstRecord *traceData) const 2002124SN/A { 2012239SN/A Addr EA; 2022132SN/A Fault fault = NoFault; 2032239SN/A 2042239SN/A %(fp_enable_check)s; 2052239SN/A %(op_decl)s; 2062239SN/A %(op_rd)s; 2072239SN/A EA = xc->getEA(); 2082239SN/A 2092239SN/A if (fault == NoFault) { 2102239SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 2112239SN/A %(code)s; 2122239SN/A } 2132239SN/A 2142239SN/A if (fault == NoFault) { 2152239SN/A %(op_wb)s; 2162239SN/A } 2172239SN/A 2182124SN/A return fault; 2192124SN/A } 2202124SN/A}}; 2212124SN/A 2222124SN/A 2232124SN/Adef template LoadExecute {{ 2242132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2252124SN/A Trace::InstRecord *traceData) const 2262124SN/A { 2272124SN/A Addr EA; 2282132SN/A Fault fault = NoFault; 2292124SN/A 2302124SN/A %(fp_enable_check)s; 2312124SN/A %(op_decl)s; 2322124SN/A %(op_rd)s; 2332124SN/A %(ea_code)s; 2342124SN/A 2352124SN/A if (fault == NoFault) { 2362124SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 2372124SN/A %(memacc_code)s; 2382124SN/A } 2392124SN/A 2402124SN/A if (fault == NoFault) { 2412124SN/A %(op_wb)s; 2422124SN/A } 2432124SN/A 2442124SN/A return fault; 2452124SN/A } 2462124SN/A}}; 2472124SN/A 2482124SN/A 2492124SN/Adef template LoadInitiateAcc {{ 2502132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2512124SN/A Trace::InstRecord *traceData) const 2522124SN/A { 2532239SN/A Addr EA; 2542132SN/A Fault fault = NoFault; 2552239SN/A 2562239SN/A %(fp_enable_check)s; 2572239SN/A %(op_src_decl)s; 2582239SN/A %(op_rd)s; 2592239SN/A %(ea_code)s; 2602239SN/A 2612239SN/A if (fault == NoFault) { 2622239SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 2632239SN/A } 2642239SN/A 2652124SN/A return fault; 2662124SN/A } 2672124SN/A}}; 2682124SN/A 2692124SN/A 2702124SN/Adef template LoadCompleteAcc {{ 2712132SN/A Fault %(class_name)s::completeAcc(uint8_t *data, 2722124SN/A %(CPU_exec_context)s *xc, 2732124SN/A Trace::InstRecord *traceData) const 2742124SN/A { 2752132SN/A Fault fault = NoFault; 2762239SN/A 2772239SN/A %(fp_enable_check)s; 2782506SN/A %(op_decl)s; 2792239SN/A 2802239SN/A memcpy(&Mem, data, sizeof(Mem)); 2812239SN/A 2822239SN/A if (fault == NoFault) { 2832239SN/A %(memacc_code)s; 2842239SN/A } 2852239SN/A 2862239SN/A if (fault == NoFault) { 2872239SN/A %(op_wb)s; 2882239SN/A } 2892239SN/A 2902124SN/A return fault; 2912124SN/A } 2922124SN/A}}; 2932124SN/A 2942124SN/A 2952124SN/Adef template StoreMemAccExecute {{ 2962132SN/A Fault 2972124SN/A %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 2982124SN/A Trace::InstRecord *traceData) const 2992124SN/A { 3002239SN/A Addr EA; 3012132SN/A Fault fault = NoFault; 3022239SN/A uint64_t write_result = 0; 3032239SN/A 3042239SN/A %(fp_enable_check)s; 3052239SN/A %(op_decl)s; 3062239SN/A %(op_rd)s; 3072239SN/A EA = xc->getEA(); 3082239SN/A 3092239SN/A if (fault == NoFault) { 3102239SN/A %(code)s; 3112239SN/A } 3122239SN/A 3132239SN/A if (fault == NoFault) { 3142239SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3152239SN/A memAccessFlags, &write_result); 3162239SN/A if (traceData) { traceData->setData(Mem); } 3172239SN/A } 3182239SN/A 3192239SN/A if (fault == NoFault) { 3202239SN/A %(postacc_code)s; 3212239SN/A } 3222239SN/A 3232239SN/A if (fault == NoFault) { 3242239SN/A %(op_wb)s; 3252239SN/A } 3262239SN/A 3272124SN/A return fault; 3282124SN/A } 3292124SN/A}}; 3302124SN/A 3312124SN/A 3322124SN/Adef template StoreExecute {{ 3332132SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3342124SN/A Trace::InstRecord *traceData) const 3352124SN/A { 3362124SN/A Addr EA; 3372132SN/A Fault fault = NoFault; 3382124SN/A uint64_t write_result = 0; 3392124SN/A 3402124SN/A %(fp_enable_check)s; 3412124SN/A %(op_decl)s; 3422124SN/A %(op_rd)s; 3432124SN/A %(ea_code)s; 3442124SN/A 3452124SN/A if (fault == NoFault) { 3462124SN/A %(memacc_code)s; 3472124SN/A } 3482124SN/A 3492124SN/A if (fault == NoFault) { 3502124SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3512124SN/A memAccessFlags, &write_result); 3522124SN/A if (traceData) { traceData->setData(Mem); } 3532124SN/A } 3542124SN/A 3552124SN/A if (fault == NoFault) { 3562124SN/A %(postacc_code)s; 3572124SN/A } 3582124SN/A 3592124SN/A if (fault == NoFault) { 3602124SN/A %(op_wb)s; 3612124SN/A } 3622124SN/A 3632124SN/A return fault; 3642124SN/A } 3652124SN/A}}; 3662124SN/A 3672124SN/Adef template StoreInitiateAcc {{ 3682132SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3692124SN/A Trace::InstRecord *traceData) const 3702124SN/A { 3712239SN/A Addr EA; 3722132SN/A Fault fault = NoFault; 3732239SN/A uint64_t write_result = 0; 3742239SN/A 3752239SN/A %(fp_enable_check)s; 3762506SN/A %(op_decl)s; 3772239SN/A %(op_rd)s; 3782239SN/A %(ea_code)s; 3792239SN/A 3802239SN/A if (fault == NoFault) { 3812239SN/A %(memacc_code)s; 3822239SN/A } 3832239SN/A 3842239SN/A if (fault == NoFault) { 3852239SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3862239SN/A memAccessFlags, &write_result); 3872239SN/A if (traceData) { traceData->setData(Mem); } 3882239SN/A } 3892239SN/A 3902124SN/A return fault; 3912124SN/A } 3922124SN/A}}; 3932124SN/A 3942124SN/A 3952124SN/Adef template StoreCompleteAcc {{ 3962132SN/A Fault %(class_name)s::completeAcc(uint8_t *data, 3972124SN/A %(CPU_exec_context)s *xc, 3982124SN/A Trace::InstRecord *traceData) const 3992124SN/A { 4002132SN/A Fault fault = NoFault; 4012239SN/A uint64_t write_result = 0; 4022239SN/A 4032239SN/A %(fp_enable_check)s; 4042239SN/A %(op_dest_decl)s; 4052239SN/A 4062239SN/A memcpy(&write_result, data, sizeof(write_result)); 4072239SN/A 4082239SN/A if (fault == NoFault) { 4092239SN/A %(postacc_code)s; 4102239SN/A } 4112239SN/A 4122239SN/A if (fault == NoFault) { 4132239SN/A %(op_wb)s; 4142239SN/A } 4152239SN/A 4162124SN/A return fault; 4172124SN/A } 4182124SN/A}}; 4192124SN/A 4202686Sksewell@umich.edu 4212686Sksewell@umich.edudef template MiscMemAccExecute {{ 4222686Sksewell@umich.edu Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 4232686Sksewell@umich.edu Trace::InstRecord *traceData) const 4242686Sksewell@umich.edu { 4252686Sksewell@umich.edu Addr EA; 4262686Sksewell@umich.edu Fault fault = NoFault; 4272686Sksewell@umich.edu 4282686Sksewell@umich.edu %(fp_enable_check)s; 4292686Sksewell@umich.edu %(op_decl)s; 4302686Sksewell@umich.edu %(op_rd)s; 4312686Sksewell@umich.edu EA = xc->getEA(); 4322686Sksewell@umich.edu 4332686Sksewell@umich.edu if (fault == NoFault) { 4342686Sksewell@umich.edu %(code)s; 4352686Sksewell@umich.edu } 4362686Sksewell@umich.edu 4372686Sksewell@umich.edu return NoFault; 4382686Sksewell@umich.edu } 4392686Sksewell@umich.edu}}; 4402686Sksewell@umich.edu 4412686Sksewell@umich.edudef template MiscExecute {{ 4422686Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 4432686Sksewell@umich.edu Trace::InstRecord *traceData) const 4442686Sksewell@umich.edu { 4452686Sksewell@umich.edu Addr EA; 4462686Sksewell@umich.edu Fault fault = NoFault; 4472686Sksewell@umich.edu 4482686Sksewell@umich.edu %(fp_enable_check)s; 4492686Sksewell@umich.edu %(op_decl)s; 4502686Sksewell@umich.edu %(op_rd)s; 4512686Sksewell@umich.edu %(ea_code)s; 4522686Sksewell@umich.edu 4532686Sksewell@umich.edu if (fault == NoFault) { 4542686Sksewell@umich.edu %(memacc_code)s; 4552686Sksewell@umich.edu } 4562686Sksewell@umich.edu 4572686Sksewell@umich.edu return NoFault; 4582686Sksewell@umich.edu } 4592686Sksewell@umich.edu}}; 4602686Sksewell@umich.edu 4612686Sksewell@umich.edudef template MiscInitiateAcc {{ 4622686Sksewell@umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4632686Sksewell@umich.edu Trace::InstRecord *traceData) const 4642686Sksewell@umich.edu { 4652686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4662686Sksewell@umich.edu return NoFault; 4672686Sksewell@umich.edu } 4682686Sksewell@umich.edu}}; 4692686Sksewell@umich.edu 4702686Sksewell@umich.edu 4712686Sksewell@umich.edudef template MiscCompleteAcc {{ 4722686Sksewell@umich.edu Fault %(class_name)s::completeAcc(uint8_t *data, 4732686Sksewell@umich.edu %(CPU_exec_context)s *xc, 4742686Sksewell@umich.edu Trace::InstRecord *traceData) const 4752686Sksewell@umich.edu { 4762686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4772686Sksewell@umich.edu 4782686Sksewell@umich.edu return NoFault; 4792686Sksewell@umich.edu } 4802686Sksewell@umich.edu}}; 4812686Sksewell@umich.edu 4822124SN/A// load instructions use Rt as dest, so check for 4832686Sksewell@umich.edu// Rt == 0 to detect nops 4842124SN/Adef template LoadNopCheckDecode {{ 4852124SN/A { 4862124SN/A MipsStaticInst *i = new %(class_name)s(machInst); 4872124SN/A if (RT == 0) { 4882124SN/A i = makeNop(i); 4892124SN/A } 4902124SN/A return i; 4912124SN/A } 4922124SN/A}}; 4932124SN/A 4942124SN/Adef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4952124SN/A mem_flags = [], inst_flags = []) {{ 4962124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4972124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4982124SN/A decode_template = LoadNopCheckDecode, 4992124SN/A exec_template_base = 'Load') 5002124SN/A}}; 5012124SN/A 5022124SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 5032124SN/A mem_flags = [], inst_flags = []) {{ 5042124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5052124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5062124SN/A exec_template_base = 'Store') 5072124SN/A}}; 5082124SN/A 5092686Sksewell@umich.edudef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5102573SN/A mem_flags = [], inst_flags = []) {{ 5112573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5122573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5132686Sksewell@umich.edu decode_template = LoadNopCheckDecode, 5142573SN/A exec_template_base = 'Load') 5152573SN/A}}; 5162573SN/A 5172686Sksewell@umich.edudef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5182573SN/A mem_flags = [], inst_flags = []) {{ 5192573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5202573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5212573SN/A exec_template_base = 'Store') 5222573SN/A}}; 5232573SN/A 5242686Sksewell@umich.edudef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5252686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5262686Sksewell@umich.edu decl_code = 'uint32_t mem_word = Mem.uw;\n' 5272686Sksewell@umich.edu decl_code += 'uint32_t unalign_addr = Rs + disp;\n' 5282686Sksewell@umich.edu decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n' 5292686Sksewell@umich.edu decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 5302686Sksewell@umich.edu decl_code += '\tbyte_offset ^= 3;\n' 5312686Sksewell@umich.edu decl_code += '#endif\n' 5322573SN/A 5332686Sksewell@umich.edu memacc_code = decl_code + memacc_code 5342686Sksewell@umich.edu 5352686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5362686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5372686Sksewell@umich.edu decode_template = LoadNopCheckDecode, 5382686Sksewell@umich.edu exec_template_base = 'Load') 5392686Sksewell@umich.edu}}; 5402686Sksewell@umich.edu 5412686Sksewell@umich.edudef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5422686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5432686Sksewell@umich.edu decl_code = 'uint32_t mem_word = 0;\n' 5442686Sksewell@umich.edu decl_code += 'uint32_t unaligned_addr = Rs + disp;\n' 5452686Sksewell@umich.edu decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n' 5462686Sksewell@umich.edu decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 5472686Sksewell@umich.edu decl_code += '\tbyte_offset ^= 3;\n' 5482686Sksewell@umich.edu decl_code += '#endif\n' 5492686Sksewell@umich.edu decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n' 5502686Sksewell@umich.edu memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 5512686Sksewell@umich.edu 5522686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5532686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5542686Sksewell@umich.edu decode_template = LoadNopCheckDecode, 5552686Sksewell@umich.edu exec_template_base = 'Store') 5562686Sksewell@umich.edu}}; 5572686Sksewell@umich.edu 5582686Sksewell@umich.edudef format Prefetch(ea_code = {{ EA = Rs + disp; }}, 5592686Sksewell@umich.edu mem_flags = [], pf_flags = [], inst_flags = []) {{ 5602686Sksewell@umich.edu pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT'] 5612686Sksewell@umich.edu pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 5622686Sksewell@umich.edu 'IsDataPrefetch', 'MemReadOp'] 5632686Sksewell@umich.edu 5642686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5652686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, 5662686Sksewell@umich.edu 'xc->prefetch(EA, memAccessFlags);', 5672686Sksewell@umich.edu pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5682686Sksewell@umich.edu 5692686Sksewell@umich.edu}}; 5702686Sksewell@umich.edu 5712686Sksewell@umich.edudef format StoreCond(memacc_code, postacc_code, 5722686Sksewell@umich.edu ea_code = {{ EA = Rs + disp; }}, 5732495SN/A mem_flags = [], inst_flags = []) {{ 5742495SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5752495SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5762495SN/A postacc_code, exec_template_base = 'Store') 5772495SN/A}}; 578