mem.isa revision 2573
12440SN/A// -*- mode:c++ -*- 22440SN/A 32440SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 42440SN/A// All rights reserved. 52440SN/A// 62440SN/A// Redistribution and use in source and binary forms, with or without 72440SN/A// modification, are permitted provided that the following conditions are 82440SN/A// met: redistributions of source code must retain the above copyright 92440SN/A// notice, this list of conditions and the following disclaimer; 102440SN/A// redistributions in binary form must reproduce the above copyright 112440SN/A// notice, this list of conditions and the following disclaimer in the 122440SN/A// documentation and/or other materials provided with the distribution; 132440SN/A// neither the name of the copyright holders nor the names of its 142440SN/A// contributors may be used to endorse or promote products derived from 152440SN/A// this software without specific prior written permission. 162440SN/A// 172440SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182440SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192440SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202440SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212440SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222440SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232440SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242440SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252440SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262440SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.eduoutput header {{ 302440SN/A /** 312440SN/A * Base class for general Mips memory-format instructions. 322440SN/A */ 332440SN/A class Memory : public MipsStaticInst 342440SN/A { 352440SN/A protected: 362440SN/A 372972Sgblack@eecs.umich.edu /// Memory request flags. See mem_req_base.hh. 382460SN/A unsigned memAccessFlags; 392440SN/A /// Pointer to EAComp object. 403120Sgblack@eecs.umich.edu const StaticInstPtr eaCompPtr; 412440SN/A /// Pointer to MemAcc object. 422440SN/A const StaticInstPtr memAccPtr; 432440SN/A 442440SN/A /// Displacement for EA calculation (signed). 452440SN/A int32_t disp; 463120Sgblack@eecs.umich.edu 472440SN/A /// Constructor 482440SN/A Memory(const char *mnem, MachInst _machInst, OpClass __opClass, 493120Sgblack@eecs.umich.edu StaticInstPtr _eaCompPtr = nullStaticInstPtr, 503120Sgblack@eecs.umich.edu StaticInstPtr _memAccPtr = nullStaticInstPtr) 512440SN/A : MipsStaticInst(mnem, _machInst, __opClass), 522440SN/A memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), 532440SN/A disp(OFFSET) 542440SN/A { 552440SN/A //If Bit 15 is 1 then Sign Extend 562440SN/A int32_t temp = disp & 0x00008000; 572440SN/A 582467SN/A if (temp > 0) { 592440SN/A disp |= 0xFFFF0000; 602440SN/A } 612440SN/A } 622440SN/A 632467SN/A std::string 642440SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 652440SN/A 662440SN/A public: 672440SN/A 682467SN/A const StaticInstPtr &eaCompInst() const { return eaCompPtr; } 692440SN/A const StaticInstPtr &memAccInst() const { return memAccPtr; } 702440SN/A }; 712440SN/A 722440SN/A}}; 732467SN/A 742440SN/A 752440SN/Aoutput decoder {{ 762440SN/A std::string 772440SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 782467SN/A { 792440SN/A return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 802440SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 812440SN/A } 822440SN/A 832440SN/A}}; 842467SN/A 852440SN/Adef format LoadAddress(code) {{ 862440SN/A iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code)) 872440SN/A header_output = BasicDeclare.subst(iop) 882467SN/A decoder_output = BasicConstructor.subst(iop) 892440SN/A decode_block = BasicDecode.subst(iop) 902440SN/A exec_output = BasicExecute.subst(iop) 912440SN/A}}; 922440SN/A 932440SN/A 942467SN/Adef template LoadStoreDeclare {{ 952440SN/A /** 962440SN/A * Static instruction class for "%(mnemonic)s". 972440SN/A */ 982467SN/A class %(class_name)s : public %(base_class)s 992440SN/A { 1002440SN/A protected: 1012440SN/A 1022440SN/A /** 1032440SN/A * "Fake" effective address computation class for "%(mnemonic)s". 1042440SN/A */ 1052440SN/A class EAComp : public %(base_class)s 1062440SN/A { 1072440SN/A public: 1082440SN/A /// Constructor 1092440SN/A EAComp(MachInst machInst); 1102440SN/A 1112440SN/A %(BasicExecDeclare)s 1122440SN/A }; 1132680Sktlim@umich.edu 1142440SN/A /** 1152680Sktlim@umich.edu * "Fake" memory access instruction class for "%(mnemonic)s". 1162680Sktlim@umich.edu */ 1172440SN/A class MemAcc : public %(base_class)s 1182440SN/A { 1192440SN/A public: 1202467SN/A /// Constructor 1212440SN/A MemAcc(MachInst machInst); 1222440SN/A 1232440SN/A %(BasicExecDeclare)s 1242440SN/A }; 1252440SN/A 1262440SN/A public: 1272467SN/A 1282440SN/A /// Constructor. 1292440SN/A %(class_name)s(MachInst machInst); 1302467SN/A 1312440SN/A %(BasicExecDeclare)s 1322440SN/A 1332467SN/A %(InitiateAccDeclare)s 1342467SN/A 1352440SN/A %(CompleteAccDeclare)s 1362440SN/A }; 1372467SN/A}}; 1382440SN/A 1392467SN/A 1402440SN/Adef template InitiateAccDeclare {{ 1412440SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1422440SN/A}}; 1432467SN/A 1442440SN/A 1452440SN/Adef template CompleteAccDeclare {{ 1462440SN/A Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1472680Sktlim@umich.edu}}; 1482680Sktlim@umich.edu 1492440SN/A 1502440SN/Adef template LoadStoreConstructor {{ 1512440SN/A /** TODO: change op_class to AddrGenOp or something (requires 1522680Sktlim@umich.edu * creating new member of OpClass enum in op_class.hh, updating 1532440SN/A * config files, etc.). */ 1542680Sktlim@umich.edu inline %(class_name)s::EAComp::EAComp(MachInst machInst) 1552680Sktlim@umich.edu : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) 1562440SN/A { 1572440SN/A %(ea_constructor)s; 1582440SN/A } 1592440SN/A 1602440SN/A inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) 161 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) 162 { 163 %(memacc_constructor)s; 164 } 165 166 inline %(class_name)s::%(class_name)s(MachInst machInst) 167 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 168 new EAComp(machInst), new MemAcc(machInst)) 169 { 170 %(constructor)s; 171 } 172}}; 173 174 175def template EACompExecute {{ 176 Fault 177 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, 178 Trace::InstRecord *traceData) const 179 { 180 Addr EA; 181 Fault fault = NoFault; 182 183 %(fp_enable_check)s; 184 %(op_decl)s; 185 %(op_rd)s; 186 %(code)s; 187 188 if (fault == NoFault) { 189 %(op_wb)s; 190 xc->setEA(EA); 191 } 192 193 return fault; 194 } 195}}; 196 197def template LoadMemAccExecute {{ 198 Fault 199 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 200 Trace::InstRecord *traceData) const 201 { 202 Addr EA; 203 Fault fault = NoFault; 204 205 %(fp_enable_check)s; 206 %(op_decl)s; 207 %(op_rd)s; 208 EA = xc->getEA(); 209 210 if (fault == NoFault) { 211 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 212 %(code)s; 213 } 214 215 if (fault == NoFault) { 216 %(op_wb)s; 217 } 218 219 return fault; 220 } 221}}; 222 223 224def template LoadExecute {{ 225 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 226 Trace::InstRecord *traceData) const 227 { 228 Addr EA; 229 Fault fault = NoFault; 230 231 %(fp_enable_check)s; 232 %(op_decl)s; 233 %(op_rd)s; 234 %(ea_code)s; 235 236 if (fault == NoFault) { 237 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 238 %(memacc_code)s; 239 } 240 241 if (fault == NoFault) { 242 %(op_wb)s; 243 } 244 245 return fault; 246 } 247}}; 248 249 250def template LoadInitiateAcc {{ 251 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 252 Trace::InstRecord *traceData) const 253 { 254 Addr EA; 255 Fault fault = NoFault; 256 257 %(fp_enable_check)s; 258 %(op_src_decl)s; 259 %(op_rd)s; 260 %(ea_code)s; 261 262 if (fault == NoFault) { 263 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 264 } 265 266 return fault; 267 } 268}}; 269 270 271def template LoadCompleteAcc {{ 272 Fault %(class_name)s::completeAcc(uint8_t *data, 273 %(CPU_exec_context)s *xc, 274 Trace::InstRecord *traceData) const 275 { 276 Fault fault = NoFault; 277 278 %(fp_enable_check)s; 279 %(op_decl)s; 280 281 memcpy(&Mem, data, sizeof(Mem)); 282 283 if (fault == NoFault) { 284 %(memacc_code)s; 285 } 286 287 if (fault == NoFault) { 288 %(op_wb)s; 289 } 290 291 return fault; 292 } 293}}; 294 295 296def template StoreMemAccExecute {{ 297 Fault 298 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 299 Trace::InstRecord *traceData) const 300 { 301 Addr EA; 302 Fault fault = NoFault; 303 uint64_t write_result = 0; 304 305 %(fp_enable_check)s; 306 %(op_decl)s; 307 %(op_rd)s; 308 EA = xc->getEA(); 309 310 if (fault == NoFault) { 311 %(code)s; 312 } 313 314 if (fault == NoFault) { 315 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 316 memAccessFlags, &write_result); 317 if (traceData) { traceData->setData(Mem); } 318 } 319 320 if (fault == NoFault) { 321 %(postacc_code)s; 322 } 323 324 if (fault == NoFault) { 325 %(op_wb)s; 326 } 327 328 return fault; 329 } 330}}; 331 332 333def template StoreExecute {{ 334 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 335 Trace::InstRecord *traceData) const 336 { 337 Addr EA; 338 Fault fault = NoFault; 339 uint64_t write_result = 0; 340 341 %(fp_enable_check)s; 342 %(op_decl)s; 343 %(op_rd)s; 344 %(ea_code)s; 345 346 if (fault == NoFault) { 347 %(memacc_code)s; 348 } 349 350 if (fault == NoFault) { 351 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 352 memAccessFlags, &write_result); 353 if (traceData) { traceData->setData(Mem); } 354 } 355 356 if (fault == NoFault) { 357 %(postacc_code)s; 358 } 359 360 if (fault == NoFault) { 361 %(op_wb)s; 362 } 363 364 return fault; 365 } 366}}; 367 368def template StoreInitiateAcc {{ 369 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 370 Trace::InstRecord *traceData) const 371 { 372 Addr EA; 373 Fault fault = NoFault; 374 uint64_t write_result = 0; 375 376 %(fp_enable_check)s; 377 %(op_decl)s; 378 %(op_rd)s; 379 %(ea_code)s; 380 381 if (fault == NoFault) { 382 %(memacc_code)s; 383 } 384 385 if (fault == NoFault) { 386 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 387 memAccessFlags, &write_result); 388 if (traceData) { traceData->setData(Mem); } 389 } 390 391 return fault; 392 } 393}}; 394 395 396def template StoreCompleteAcc {{ 397 Fault %(class_name)s::completeAcc(uint8_t *data, 398 %(CPU_exec_context)s *xc, 399 Trace::InstRecord *traceData) const 400 { 401 Fault fault = NoFault; 402 uint64_t write_result = 0; 403 404 %(fp_enable_check)s; 405 %(op_dest_decl)s; 406 407 memcpy(&write_result, data, sizeof(write_result)); 408 409 if (fault == NoFault) { 410 %(postacc_code)s; 411 } 412 413 if (fault == NoFault) { 414 %(op_wb)s; 415 } 416 417 return fault; 418 } 419}}; 420 421// load instructions use Rt as dest, so check for 422// Rt == 31 to detect nops 423def template LoadNopCheckDecode {{ 424 { 425 MipsStaticInst *i = new %(class_name)s(machInst); 426 if (RT == 0) { 427 i = makeNop(i); 428 } 429 return i; 430 } 431}}; 432 433def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 434 mem_flags = [], inst_flags = []) {{ 435 (header_output, decoder_output, decode_block, exec_output) = \ 436 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 437 decode_template = LoadNopCheckDecode, 438 exec_template_base = 'Load') 439}}; 440 441 442def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 443 mem_flags = [], inst_flags = []) {{ 444 (header_output, decoder_output, decode_block, exec_output) = \ 445 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 446 exec_template_base = 'Store') 447}}; 448 449//FP loads are offloaded to these formats for now ... 450def format LoadFloatMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 451 mem_flags = [], inst_flags = []) {{ 452 (header_output, decoder_output, decode_block, exec_output) = \ 453 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 454 decode_template = BasicDecode, 455 exec_template_base = 'Load') 456}}; 457 458 459def format StoreFloatMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 460 mem_flags = [], inst_flags = []) {{ 461 (header_output, decoder_output, decode_block, exec_output) = \ 462 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 463 exec_template_base = 'Store') 464}}; 465 466 467def format UnalignedStore(memacc_code, postacc_code, 468 ea_code = {{ EA = Rb + disp; }}, 469 mem_flags = [], inst_flags = []) {{ 470 (header_output, decoder_output, decode_block, exec_output) = \ 471 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 472 postacc_code, exec_template_base = 'Store') 473}}; 474