mem.isa revision 2239
12124SN/A// -*- mode:c++ -*- 22124SN/A 35268Sksewell@umich.edu// Copyright (c) 2003-2005 The Regents of The University of Michigan 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu 295268Sksewell@umich.eduoutput header {{ 305268Sksewell@umich.edu /** 312022SN/A * Base class for general Mips memory-format instructions. 322649Ssaidi@eecs.umich.edu */ 332649Ssaidi@eecs.umich.edu class Memory : public MipsStaticInst 342706Sksewell@umich.edu { 352649Ssaidi@eecs.umich.edu protected: 362649Ssaidi@eecs.umich.edu 372022SN/A /// Memory request flags. See mem_req_base.hh. 382124SN/A unsigned memAccessFlags; 392124SN/A /// Pointer to EAComp object. 402124SN/A const StaticInstPtr eaCompPtr; 412124SN/A /// Pointer to MemAcc object. 422124SN/A const StaticInstPtr memAccPtr; 432124SN/A 442124SN/A /// Displacement for EA calculation (signed). 455736Snate@binkert.org int32_t disp; 462239SN/A 472124SN/A /// Constructor 482124SN/A Memory(const char *mnem, MachInst _machInst, OpClass __opClass, 492124SN/A StaticInstPtr _eaCompPtr = nullStaticInstPtr, 502124SN/A StaticInstPtr _memAccPtr = nullStaticInstPtr) 516207Sksewell@umich.edu : MipsStaticInst(mnem, _machInst, __opClass), 522124SN/A memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), 532742Sksewell@umich.edu disp(OFFSET) 542022SN/A { 552124SN/A //If Bit 15 is 1 then Sign Extend 562022SN/A int32_t temp = disp & 0x00008000; 572124SN/A 582124SN/A if (temp > 0) { 592124SN/A disp |= 0xFFFF0000; 602124SN/A } 612742Sksewell@umich.edu } 622742Sksewell@umich.edu 632742Sksewell@umich.edu std::string 642742Sksewell@umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 652742Sksewell@umich.edu 662742Sksewell@umich.edu public: 672742Sksewell@umich.edu 682742Sksewell@umich.edu const StaticInstPtr &eaCompInst() const { return eaCompPtr; } 696207Sksewell@umich.edu const StaticInstPtr &memAccInst() const { return memAccPtr; } 706207Sksewell@umich.edu }; 712742Sksewell@umich.edu 722742Sksewell@umich.edu}}; 732742Sksewell@umich.edu 742742Sksewell@umich.edu 752742Sksewell@umich.eduoutput decoder {{ 762742Sksewell@umich.edu std::string 772022SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 782022SN/A { 792124SN/A return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 802022SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 812124SN/A } 822124SN/A 832124SN/A}}; 842742Sksewell@umich.edu 852239SN/Adef format LoadAddress(code) {{ 862124SN/A iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code)) 872124SN/A header_output = BasicDeclare.subst(iop) 882742Sksewell@umich.edu decoder_output = BasicConstructor.subst(iop) 892742Sksewell@umich.edu decode_block = BasicDecode.subst(iop) 902742Sksewell@umich.edu exec_output = BasicExecute.subst(iop) 912742Sksewell@umich.edu}}; 922742Sksewell@umich.edu 932742Sksewell@umich.edu 942742Sksewell@umich.edudef template LoadStoreDeclare {{ 952742Sksewell@umich.edu /** 964661Sksewell@umich.edu * Static instruction class for "%(mnemonic)s". 974661Sksewell@umich.edu */ 984661Sksewell@umich.edu class %(class_name)s : public %(base_class)s 999554Sandreas.hansson@arm.com { 1009554Sandreas.hansson@arm.com protected: 1019554Sandreas.hansson@arm.com 1029554Sandreas.hansson@arm.com /** 1039554Sandreas.hansson@arm.com * "Fake" effective address computation class for "%(mnemonic)s". 1044661Sksewell@umich.edu */ 1054661Sksewell@umich.edu class EAComp : public %(base_class)s 1064661Sksewell@umich.edu { 1074661Sksewell@umich.edu public: 10810196SCurtis.Dunham@arm.com /// Constructor 1094661Sksewell@umich.edu EAComp(MachInst machInst); 1104661Sksewell@umich.edu 1115222Sksewell@umich.edu %(BasicExecDeclare)s 1124661Sksewell@umich.edu }; 1134661Sksewell@umich.edu 1145222Sksewell@umich.edu /** 1154661Sksewell@umich.edu * "Fake" memory access instruction class for "%(mnemonic)s". 1164661Sksewell@umich.edu */ 1175222Sksewell@umich.edu class MemAcc : public %(base_class)s 1184661Sksewell@umich.edu { 1194661Sksewell@umich.edu public: 1205222Sksewell@umich.edu /// Constructor 1214661Sksewell@umich.edu MemAcc(MachInst machInst); 1224661Sksewell@umich.edu 1234661Sksewell@umich.edu %(BasicExecDeclare)s 1244661Sksewell@umich.edu }; 1254661Sksewell@umich.edu 1264661Sksewell@umich.edu public: 1274661Sksewell@umich.edu 1284661Sksewell@umich.edu /// Constructor. 1294661Sksewell@umich.edu %(class_name)s(MachInst machInst); 1304661Sksewell@umich.edu 1314661Sksewell@umich.edu %(BasicExecDeclare)s 1322022SN/A 1332022SN/A %(InitiateAccDeclare)s 1342124SN/A 1352124SN/A %(CompleteAccDeclare)s 1362124SN/A }; 1372124SN/A}}; 1382124SN/A 1392124SN/A 1402124SN/Adef template InitiateAccDeclare {{ 1412124SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1422124SN/A}}; 1434661Sksewell@umich.edu 1442124SN/A 1452124SN/Adef template CompleteAccDeclare {{ 1462124SN/A Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1476207Sksewell@umich.edu}}; 1486207Sksewell@umich.edu 1492124SN/A 1502124SN/Adef template LoadStoreConstructor {{ 1512124SN/A /** TODO: change op_class to AddrGenOp or something (requires 1522124SN/A * creating new member of OpClass enum in op_class.hh, updating 1532022SN/A * config files, etc.). */ 1542022SN/A inline %(class_name)s::EAComp::EAComp(MachInst machInst) 1556207Sksewell@umich.edu : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) 1566207Sksewell@umich.edu { 1576207Sksewell@umich.edu %(ea_constructor)s; 1582124SN/A } 1592124SN/A 1602132SN/A inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) 1612022SN/A : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) 1622124SN/A { 1632124SN/A %(memacc_constructor)s; 1642124SN/A } 1654661Sksewell@umich.edu 1662124SN/A inline %(class_name)s::%(class_name)s(MachInst machInst) 1672124SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 1686207Sksewell@umich.edu new EAComp(machInst), new MemAcc(machInst)) 16910184SCurtis.Dunham@arm.com { 1706207Sksewell@umich.edu %(constructor)s; 1712124SN/A } 1723953Sstever@eecs.umich.edu}}; 1732124SN/A 1743953Sstever@eecs.umich.edu 1752124SN/Adef template EACompExecute {{ 1763953Sstever@eecs.umich.edu Fault 1772124SN/A %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, 1782132SN/A Trace::InstRecord *traceData) const 17910196SCurtis.Dunham@arm.com { 1802124SN/A Addr EA; 1812124SN/A Fault fault = NoFault; 1822124SN/A 1832132SN/A %(fp_enable_check)s; 1842124SN/A %(op_decl)s; 1855222Sksewell@umich.edu %(op_rd)s; 1865222Sksewell@umich.edu %(code)s; 1875222Sksewell@umich.edu 1885222Sksewell@umich.edu if (fault == NoFault) { 1895222Sksewell@umich.edu %(op_wb)s; 1905222Sksewell@umich.edu xc->setEA(EA); 1915222Sksewell@umich.edu } 1922124SN/A 1932124SN/A return fault; 1943953Sstever@eecs.umich.edu } 1952124SN/A}}; 1964661Sksewell@umich.edu 1972124SN/Adef template LoadMemAccExecute {{ 1982124SN/A Fault 1992124SN/A %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 2002124SN/A Trace::InstRecord *traceData) const 2012124SN/A { 2022124SN/A Addr EA; 2032124SN/A Fault fault = NoFault; 2042124SN/A 2052124SN/A %(fp_enable_check)s; 20610196SCurtis.Dunham@arm.com %(op_decl)s; 2072124SN/A %(op_rd)s; 2082124SN/A EA = xc->getEA(); 2092124SN/A 2102132SN/A if (fault == NoFault) { 2112124SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 2125222Sksewell@umich.edu %(code)s; 2135222Sksewell@umich.edu } 2145222Sksewell@umich.edu 2155222Sksewell@umich.edu if (fault == NoFault) { 2165222Sksewell@umich.edu %(op_wb)s; 2175222Sksewell@umich.edu } 2185222Sksewell@umich.edu 2192124SN/A return fault; 2202124SN/A } 2212124SN/A}}; 2222124SN/A 2232124SN/A 2248442Sgblack@eecs.umich.edudef template LoadExecute {{ 2252124SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2262124SN/A Trace::InstRecord *traceData) const 2272124SN/A { 2282124SN/A Addr EA; 2292124SN/A Fault fault = NoFault; 2302124SN/A 2312124SN/A %(fp_enable_check)s; 2322124SN/A %(op_decl)s; 2332124SN/A %(op_rd)s; 2342124SN/A %(ea_code)s; 2352124SN/A 2362124SN/A if (fault == NoFault) { 2372124SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 23810196SCurtis.Dunham@arm.com %(memacc_code)s; 2392124SN/A } 2402124SN/A 2412239SN/A if (fault == NoFault) { 2422132SN/A %(op_wb)s; 2432239SN/A } 2445222Sksewell@umich.edu 2455222Sksewell@umich.edu return fault; 2465222Sksewell@umich.edu } 2475222Sksewell@umich.edu}}; 2485222Sksewell@umich.edu 2495222Sksewell@umich.edu 2505222Sksewell@umich.edudef template LoadInitiateAcc {{ 2512239SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2522239SN/A Trace::InstRecord *traceData) const 2532239SN/A { 2542239SN/A Addr EA; 2552239SN/A Fault fault = NoFault; 25611303Ssteve.reinhardt@amd.com 2572239SN/A %(fp_enable_check)s; 2582239SN/A %(op_src_decl)s; 2592124SN/A %(op_rd)s; 2602124SN/A %(ea_code)s; 2612124SN/A 2622124SN/A if (fault == NoFault) { 2632124SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 2644661Sksewell@umich.edu } 26510196SCurtis.Dunham@arm.com 2662124SN/A return fault; 2672124SN/A } 2682132SN/A}}; 2692239SN/A 2705222Sksewell@umich.edu 2715222Sksewell@umich.edudef template LoadCompleteAcc {{ 2725222Sksewell@umich.edu Fault %(class_name)s::completeAcc(uint8_t *data, 2735222Sksewell@umich.edu %(CPU_exec_context)s *xc, 2745222Sksewell@umich.edu Trace::InstRecord *traceData) const 2755222Sksewell@umich.edu { 2765222Sksewell@umich.edu Fault fault = NoFault; 2772506SN/A 2784661Sksewell@umich.edu %(fp_enable_check)s; 2792239SN/A %(op_src_decl)s; 2808442Sgblack@eecs.umich.edu %(op_dest_decl)s; 2812239SN/A 2822239SN/A memcpy(&Mem, data, sizeof(Mem)); 2832239SN/A 2842239SN/A if (fault == NoFault) { 2852239SN/A %(memacc_code)s; 2862239SN/A } 2872239SN/A 2882239SN/A if (fault == NoFault) { 2892239SN/A %(op_wb)s; 2902124SN/A } 2912124SN/A 2922124SN/A return fault; 2932124SN/A } 2942124SN/A}}; 29510196SCurtis.Dunham@arm.com 2962124SN/A 2972124SN/Adef template StoreMemAccExecute {{ 2982124SN/A Fault 2992132SN/A %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 3004056Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 3014056Sstever@eecs.umich.edu { 3024056Sstever@eecs.umich.edu Addr EA; 3034056Sstever@eecs.umich.edu Fault fault = NoFault; 3044056Sstever@eecs.umich.edu uint64_t write_result = 0; 3054056Sstever@eecs.umich.edu 3064056Sstever@eecs.umich.edu %(fp_enable_check)s; 3074056Sstever@eecs.umich.edu %(op_decl)s; 3084056Sstever@eecs.umich.edu %(op_rd)s; 3094056Sstever@eecs.umich.edu EA = xc->getEA(); 3104056Sstever@eecs.umich.edu 3118442Sgblack@eecs.umich.edu if (fault == NoFault) { 3128442Sgblack@eecs.umich.edu %(code)s; 3134056Sstever@eecs.umich.edu } 3144056Sstever@eecs.umich.edu 3154056Sstever@eecs.umich.edu if (fault == NoFault) { 3164056Sstever@eecs.umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3174056Sstever@eecs.umich.edu memAccessFlags, &write_result); 3184056Sstever@eecs.umich.edu if (traceData) { traceData->setData(Mem); } 3194056Sstever@eecs.umich.edu } 3204056Sstever@eecs.umich.edu 3214056Sstever@eecs.umich.edu if (fault == NoFault) { 3224056Sstever@eecs.umich.edu %(postacc_code)s; 3234056Sstever@eecs.umich.edu } 3244056Sstever@eecs.umich.edu 3254056Sstever@eecs.umich.edu if (fault == NoFault) { 3264056Sstever@eecs.umich.edu %(op_wb)s; 3275222Sksewell@umich.edu } 3285222Sksewell@umich.edu 32910196SCurtis.Dunham@arm.com return fault; 3305222Sksewell@umich.edu } 3315222Sksewell@umich.edu}}; 3325222Sksewell@umich.edu 3335222Sksewell@umich.edu 3345222Sksewell@umich.edudef template StoreExecute {{ 3355222Sksewell@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3365222Sksewell@umich.edu Trace::InstRecord *traceData) const 3375222Sksewell@umich.edu { 3385222Sksewell@umich.edu Addr EA; 3395222Sksewell@umich.edu Fault fault = NoFault; 3405222Sksewell@umich.edu uint64_t write_result = 0; 3415222Sksewell@umich.edu 3425222Sksewell@umich.edu %(fp_enable_check)s; 3435222Sksewell@umich.edu %(op_decl)s; 3445222Sksewell@umich.edu %(op_rd)s; 3455222Sksewell@umich.edu %(ea_code)s; 3465222Sksewell@umich.edu 3478442Sgblack@eecs.umich.edu if (fault == NoFault) { 3488442Sgblack@eecs.umich.edu %(memacc_code)s; 3495222Sksewell@umich.edu } 3505222Sksewell@umich.edu 3515222Sksewell@umich.edu if (fault == NoFault) { 3525222Sksewell@umich.edu fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3535222Sksewell@umich.edu memAccessFlags, &write_result); 3545222Sksewell@umich.edu if (traceData) { traceData->setData(Mem); } 3555222Sksewell@umich.edu } 3565222Sksewell@umich.edu 3575222Sksewell@umich.edu if (fault == NoFault) { 3585222Sksewell@umich.edu %(postacc_code)s; 3595222Sksewell@umich.edu } 3605222Sksewell@umich.edu 3615222Sksewell@umich.edu if (fault == NoFault) { 3625222Sksewell@umich.edu %(op_wb)s; 3634056Sstever@eecs.umich.edu } 36410196SCurtis.Dunham@arm.com 3654056Sstever@eecs.umich.edu return fault; 3664056Sstever@eecs.umich.edu } 3674056Sstever@eecs.umich.edu}}; 3684056Sstever@eecs.umich.edu 3692124SN/Adef template StoreInitiateAcc {{ 3702124SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3712124SN/A Trace::InstRecord *traceData) const 3722124SN/A { 3732124SN/A Addr EA; 3742124SN/A Fault fault = NoFault; 3752124SN/A uint64_t write_result = 0; 3762124SN/A 3772124SN/A %(fp_enable_check)s; 3782124SN/A %(op_src_decl)s; 3792124SN/A %(op_dest_decl)s; 3802124SN/A %(op_rd)s; 3818442Sgblack@eecs.umich.edu %(ea_code)s; 3828442Sgblack@eecs.umich.edu 3832124SN/A if (fault == NoFault) { 3842124SN/A %(memacc_code)s; 3852124SN/A } 3862124SN/A 3872124SN/A if (fault == NoFault) { 3882124SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3892124SN/A memAccessFlags, &write_result); 3902124SN/A if (traceData) { traceData->setData(Mem); } 3912124SN/A } 3922124SN/A 3932124SN/A return fault; 3942124SN/A } 3952124SN/A}}; 3962124SN/A 3972124SN/A 39810196SCurtis.Dunham@arm.comdef template StoreCompleteAcc {{ 3992124SN/A Fault %(class_name)s::completeAcc(uint8_t *data, 4002124SN/A %(CPU_exec_context)s *xc, 4012239SN/A Trace::InstRecord *traceData) const 4022132SN/A { 4032239SN/A Fault fault = NoFault; 4042239SN/A uint64_t write_result = 0; 4052506SN/A 4062239SN/A %(fp_enable_check)s; 4072239SN/A %(op_dest_decl)s; 4082239SN/A 4092239SN/A memcpy(&write_result, data, sizeof(write_result)); 4102239SN/A 4112239SN/A if (fault == NoFault) { 4122239SN/A %(postacc_code)s; 4132239SN/A } 4148442Sgblack@eecs.umich.edu 4158442Sgblack@eecs.umich.edu if (fault == NoFault) { 4162239SN/A %(op_wb)s; 4172239SN/A } 4182124SN/A 4192124SN/A return fault; 4202124SN/A } 4212124SN/A}}; 4222124SN/A 4232124SN/A// load instructions use Rt as dest, so check for 4244661Sksewell@umich.edu// Rt == 31 to detect nops 42510196SCurtis.Dunham@arm.comdef template LoadNopCheckDecode {{ 4262124SN/A { 4272124SN/A MipsStaticInst *i = new %(class_name)s(machInst); 4287712Sgblack@eecs.umich.edu if (RT == 0) { 4292935Sksewell@umich.edu i = makeNop(i); 4302935Sksewell@umich.edu } 4312935Sksewell@umich.edu return i; 4322935Sksewell@umich.edu } 4334661Sksewell@umich.edu}}; 43410196SCurtis.Dunham@arm.com 4352935Sksewell@umich.edudef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4362935Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 4372935Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 4382935Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4392935Sksewell@umich.edu decode_template = LoadNopCheckDecode, 4402935Sksewell@umich.edu exec_template_base = 'Load') 4412935Sksewell@umich.edu}}; 4424055Ssaidi@eecs.umich.edu 4432239SN/A 4442239SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4452239SN/A mem_flags = [], inst_flags = []) {{ 4462239SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4472239SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4482239SN/A exec_template_base = 'Store') 4492239SN/A}}; 4502239SN/A 4512239SN/A//FP loads are offloaded to these formats for now ... 4522124SN/Adef format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }}, 4532124SN/A mem_flags = [], inst_flags = []) {{ 4542124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4552124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4562686Sksewell@umich.edu decode_template = LoadNopCheckDecode, 45710196SCurtis.Dunham@arm.com exec_template_base = 'Load') 4582686Sksewell@umich.edu}}; 4592686Sksewell@umich.edu 4607725SAli.Saidi@ARM.com 4612686Sksewell@umich.edu//FP stores are offloaded to these formats for now ... 4622686Sksewell@umich.edudef format StoreMemory2(ea_code = {{ EA = Rs + disp; }},memacc_code = {{ }}, 4632686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 4642686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 4652686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4662686Sksewell@umich.edu decode_template = LoadNopCheckDecode, 4672686Sksewell@umich.edu exec_template_base = 'Store') 4682686Sksewell@umich.edu}}; 4692686Sksewell@umich.edu 4702686Sksewell@umich.edu