mem.isa revision 13233
12124SN/A// -*- mode:c++ -*- 22124SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Steve Reinhardt 305268Sksewell@umich.edu// Korey Sewell 312022SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342706Sksewell@umich.edu// Memory-format instructions 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372022SN/Aoutput header {{ 382124SN/A /** 392124SN/A * Base class for general Mips memory-format instructions. 402124SN/A */ 412124SN/A class Memory : public MipsStaticInst 422124SN/A { 432124SN/A protected: 442124SN/A /// Memory request flags. See mem_req_base.hh. 455736Snate@binkert.org Request::Flags memAccessFlags; 462239SN/A 472124SN/A /// Displacement for EA calculation (signed). 482124SN/A int32_t disp; 492124SN/A 502124SN/A /// Constructor 516207Sksewell@umich.edu Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 522124SN/A : MipsStaticInst(mnem, _machInst, __opClass), 532742Sksewell@umich.edu disp(sext<16>(OFFSET)) 542022SN/A { 552124SN/A } 562022SN/A 5712616Sgabeblack@google.com std::string generateDisassembly( 5812616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 592124SN/A }; 602124SN/A 612742Sksewell@umich.edu /** 622742Sksewell@umich.edu * Base class for a few miscellaneous memory-format insts 632742Sksewell@umich.edu * that don't interpret the disp field 642742Sksewell@umich.edu */ 652742Sksewell@umich.edu class MemoryNoDisp : public Memory 662742Sksewell@umich.edu { 672742Sksewell@umich.edu protected: 682742Sksewell@umich.edu /// Constructor 696207Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 706207Sksewell@umich.edu : Memory(mnem, _machInst, __opClass) 712742Sksewell@umich.edu { 722742Sksewell@umich.edu } 732742Sksewell@umich.edu 7412616Sgabeblack@google.com std::string generateDisassembly( 7512616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 762742Sksewell@umich.edu }; 772022SN/A}}; 782022SN/A 792124SN/A 802022SN/Aoutput decoder {{ 812124SN/A std::string 822124SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 832124SN/A { 842742Sksewell@umich.edu return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 852239SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 862124SN/A } 872124SN/A 882742Sksewell@umich.edu std::string 892742Sksewell@umich.edu MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 902742Sksewell@umich.edu { 912742Sksewell@umich.edu return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 922742Sksewell@umich.edu flags[IsFloating] ? 'f' : 'r', 932742Sksewell@umich.edu flags[IsFloating] ? FD : RD, 942742Sksewell@umich.edu RS, RT); 952742Sksewell@umich.edu } 964661Sksewell@umich.edu 974661Sksewell@umich.edu}}; 984661Sksewell@umich.edu 999554Sandreas.hansson@arm.comoutput header {{ 10012234Sgabeblack@google.com uint64_t getMemData(ExecContext *xc, Packet *packet); 1019554Sandreas.hansson@arm.com 1029554Sandreas.hansson@arm.com}}; 1039554Sandreas.hansson@arm.com 1044661Sksewell@umich.eduoutput exec {{ 1054661Sksewell@umich.edu /** return data in cases where there the size of data is only 1064661Sksewell@umich.edu known in the packet 1074661Sksewell@umich.edu */ 10812234Sgabeblack@google.com uint64_t getMemData(ExecContext *xc, Packet *packet) { 1094661Sksewell@umich.edu switch (packet->getSize()) 1104661Sksewell@umich.edu { 1115222Sksewell@umich.edu case 1: 11213233Sgabeblack@google.com return packet->getLE<uint8_t>(); 1134661Sksewell@umich.edu 1145222Sksewell@umich.edu case 2: 11513233Sgabeblack@google.com return packet->getLE<uint16_t>(); 1164661Sksewell@umich.edu 1175222Sksewell@umich.edu case 4: 11813233Sgabeblack@google.com return packet->getLE<uint32_t>(); 1194661Sksewell@umich.edu 1205222Sksewell@umich.edu case 8: 12113233Sgabeblack@google.com return packet->getLE<uint64_t>(); 1224661Sksewell@umich.edu 1234661Sksewell@umich.edu default: 1244661Sksewell@umich.edu std::cerr << "bad store data size = " << packet->getSize() << std::endl; 1254661Sksewell@umich.edu 1264661Sksewell@umich.edu assert(0); 1274661Sksewell@umich.edu return 0; 1284661Sksewell@umich.edu } 1294661Sksewell@umich.edu } 1304661Sksewell@umich.edu 1314661Sksewell@umich.edu 1322022SN/A}}; 1332022SN/A 1342124SN/Adef template LoadStoreDeclare {{ 1352124SN/A /** 1362124SN/A * Static instruction class for "%(mnemonic)s". 1372124SN/A */ 1382124SN/A class %(class_name)s : public %(base_class)s 1392124SN/A { 1402124SN/A public: 1412124SN/A 1422124SN/A /// Constructor. 1434661Sksewell@umich.edu %(class_name)s(ExtMachInst machInst); 1442124SN/A 14512616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 14612616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 14712616Sgabeblack@google.com Fault completeAcc(Packet *, ExecContext *, 14812616Sgabeblack@google.com Trace::InstRecord *) const override; 1492124SN/A }; 1502022SN/A}}; 1512022SN/A 1522124SN/A 1536207Sksewell@umich.edudef template LoadStoreConstructor {{ 15410184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst) 1556207Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1562124SN/A { 1573953Sstever@eecs.umich.edu %(constructor)s; 1582124SN/A } 1593953Sstever@eecs.umich.edu}}; 1602124SN/A 1612124SN/Adef template LoadExecute {{ 16212234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 1632124SN/A Trace::InstRecord *traceData) const 1642124SN/A { 1652124SN/A Addr EA; 1662132SN/A Fault fault = NoFault; 1672124SN/A 1685222Sksewell@umich.edu if (this->isFloating()) { 1695222Sksewell@umich.edu %(fp_enable_check)s; 1705222Sksewell@umich.edu 1715222Sksewell@umich.edu if(fault != NoFault) 1725222Sksewell@umich.edu return fault; 1735222Sksewell@umich.edu } 1745222Sksewell@umich.edu 1752124SN/A %(op_decl)s; 1762124SN/A %(op_rd)s; 1772124SN/A %(ea_code)s; 1782124SN/A 1792124SN/A if (fault == NoFault) { 1808442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 1812124SN/A %(memacc_code)s; 1822124SN/A } 1832124SN/A 1842124SN/A if (fault == NoFault) { 1852124SN/A %(op_wb)s; 1862124SN/A } 1872124SN/A 1882124SN/A return fault; 1892124SN/A } 1902124SN/A}}; 1912124SN/A 1922124SN/A 1932124SN/Adef template LoadInitiateAcc {{ 19412234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 1952124SN/A Trace::InstRecord *traceData) const 1962124SN/A { 1972239SN/A Addr EA; 1982132SN/A Fault fault = NoFault; 1992239SN/A 2005222Sksewell@umich.edu if (this->isFloating()) { 2015222Sksewell@umich.edu %(fp_enable_check)s; 2025222Sksewell@umich.edu 2035222Sksewell@umich.edu if(fault != NoFault) 2045222Sksewell@umich.edu return fault; 2055222Sksewell@umich.edu } 2065222Sksewell@umich.edu 2072239SN/A %(op_src_decl)s; 2082239SN/A %(op_rd)s; 2092239SN/A %(ea_code)s; 2102239SN/A 2112239SN/A if (fault == NoFault) { 21211303Ssteve.reinhardt@amd.com fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); 2132239SN/A } 2142239SN/A 2152124SN/A return fault; 2162124SN/A } 2172124SN/A}}; 2182124SN/A 2192124SN/Adef template LoadCompleteAcc {{ 22012234Sgabeblack@google.com Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, 2212124SN/A Trace::InstRecord *traceData) const 2222124SN/A { 2232132SN/A Fault fault = NoFault; 2242239SN/A 2255222Sksewell@umich.edu if (this->isFloating()) { 2265222Sksewell@umich.edu %(fp_enable_check)s; 2275222Sksewell@umich.edu 2285222Sksewell@umich.edu if(fault != NoFault) 2295222Sksewell@umich.edu return fault; 2305222Sksewell@umich.edu } 2315222Sksewell@umich.edu 2322506SN/A %(op_decl)s; 2334661Sksewell@umich.edu %(op_rd)s; 2342239SN/A 2358442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 2362239SN/A 2372239SN/A if (fault == NoFault) { 2382239SN/A %(memacc_code)s; 2392239SN/A } 2402239SN/A 2412239SN/A if (fault == NoFault) { 2422239SN/A %(op_wb)s; 2432239SN/A } 2442239SN/A 2452124SN/A return fault; 2462124SN/A } 2472124SN/A}}; 2482124SN/A 2492124SN/Adef template StoreExecute {{ 25012234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2512124SN/A Trace::InstRecord *traceData) const 2522124SN/A { 2532124SN/A Addr EA; 2542132SN/A Fault fault = NoFault; 2554056Sstever@eecs.umich.edu 2564056Sstever@eecs.umich.edu %(fp_enable_check)s; 2574056Sstever@eecs.umich.edu %(op_decl)s; 2584056Sstever@eecs.umich.edu %(op_rd)s; 2594056Sstever@eecs.umich.edu %(ea_code)s; 2604056Sstever@eecs.umich.edu 2614056Sstever@eecs.umich.edu if (fault == NoFault) { 2624056Sstever@eecs.umich.edu %(memacc_code)s; 2634056Sstever@eecs.umich.edu } 2644056Sstever@eecs.umich.edu 2654056Sstever@eecs.umich.edu if (fault == NoFault) { 2668442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 2678442Sgblack@eecs.umich.edu NULL); 2684056Sstever@eecs.umich.edu } 2694056Sstever@eecs.umich.edu 2704056Sstever@eecs.umich.edu if (fault == NoFault) { 2714056Sstever@eecs.umich.edu %(postacc_code)s; 2724056Sstever@eecs.umich.edu } 2734056Sstever@eecs.umich.edu 2744056Sstever@eecs.umich.edu if (fault == NoFault) { 2754056Sstever@eecs.umich.edu %(op_wb)s; 2764056Sstever@eecs.umich.edu } 2774056Sstever@eecs.umich.edu 2784056Sstever@eecs.umich.edu return fault; 2794056Sstever@eecs.umich.edu } 2804056Sstever@eecs.umich.edu}}; 2814056Sstever@eecs.umich.edu 2825222Sksewell@umich.edu 2835222Sksewell@umich.edudef template StoreFPExecute {{ 28412234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2855222Sksewell@umich.edu Trace::InstRecord *traceData) const 2865222Sksewell@umich.edu { 2875222Sksewell@umich.edu Addr EA; 2885222Sksewell@umich.edu Fault fault = NoFault; 2895222Sksewell@umich.edu 2905222Sksewell@umich.edu %(fp_enable_check)s; 2915222Sksewell@umich.edu if(fault != NoFault) 2925222Sksewell@umich.edu return fault; 2935222Sksewell@umich.edu %(op_decl)s; 2945222Sksewell@umich.edu %(op_rd)s; 2955222Sksewell@umich.edu %(ea_code)s; 2965222Sksewell@umich.edu 2975222Sksewell@umich.edu if (fault == NoFault) { 2985222Sksewell@umich.edu %(memacc_code)s; 2995222Sksewell@umich.edu } 3005222Sksewell@umich.edu 3015222Sksewell@umich.edu if (fault == NoFault) { 3028442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3038442Sgblack@eecs.umich.edu NULL); 3045222Sksewell@umich.edu } 3055222Sksewell@umich.edu 3065222Sksewell@umich.edu if (fault == NoFault) { 3075222Sksewell@umich.edu %(postacc_code)s; 3085222Sksewell@umich.edu } 3095222Sksewell@umich.edu 3105222Sksewell@umich.edu if (fault == NoFault) { 3115222Sksewell@umich.edu %(op_wb)s; 3125222Sksewell@umich.edu } 3135222Sksewell@umich.edu 3145222Sksewell@umich.edu return fault; 3155222Sksewell@umich.edu } 3165222Sksewell@umich.edu}}; 3175222Sksewell@umich.edu 3184056Sstever@eecs.umich.edudef template StoreCondExecute {{ 31912234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 3204056Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 3214056Sstever@eecs.umich.edu { 3224056Sstever@eecs.umich.edu Addr EA; 3234056Sstever@eecs.umich.edu Fault fault = NoFault; 3242124SN/A uint64_t write_result = 0; 3252124SN/A 3262124SN/A %(fp_enable_check)s; 3272124SN/A %(op_decl)s; 3282124SN/A %(op_rd)s; 3292124SN/A %(ea_code)s; 3302124SN/A 3312124SN/A if (fault == NoFault) { 3322124SN/A %(memacc_code)s; 3332124SN/A } 3342124SN/A 3352124SN/A if (fault == NoFault) { 3368442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3378442Sgblack@eecs.umich.edu &write_result); 3382124SN/A } 3392124SN/A 3402124SN/A if (fault == NoFault) { 3412124SN/A %(postacc_code)s; 3422124SN/A } 3432124SN/A 3442124SN/A if (fault == NoFault) { 3452124SN/A %(op_wb)s; 3462124SN/A } 3472124SN/A 3482124SN/A return fault; 3492124SN/A } 3502124SN/A}}; 3512124SN/A 3522124SN/Adef template StoreInitiateAcc {{ 35312234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 3542124SN/A Trace::InstRecord *traceData) const 3552124SN/A { 3562239SN/A Addr EA; 3572132SN/A Fault fault = NoFault; 3582239SN/A 3592239SN/A %(fp_enable_check)s; 3602506SN/A %(op_decl)s; 3612239SN/A %(op_rd)s; 3622239SN/A %(ea_code)s; 3632239SN/A 3642239SN/A if (fault == NoFault) { 3652239SN/A %(memacc_code)s; 3662239SN/A } 3672239SN/A 3682239SN/A if (fault == NoFault) { 3698442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3708442Sgblack@eecs.umich.edu NULL); 3712239SN/A } 3722239SN/A 3732124SN/A return fault; 3742124SN/A } 3752124SN/A}}; 3762124SN/A 3772124SN/A 3782124SN/Adef template StoreCompleteAcc {{ 3794661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 38012234Sgabeblack@google.com ExecContext *xc, 3812124SN/A Trace::InstRecord *traceData) const 3822124SN/A { 3837712Sgblack@eecs.umich.edu return NoFault; 3842935Sksewell@umich.edu } 3852935Sksewell@umich.edu}}; 3862935Sksewell@umich.edu 3872935Sksewell@umich.edudef template StoreCondCompleteAcc {{ 3884661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 38912234Sgabeblack@google.com ExecContext *xc, 3902935Sksewell@umich.edu Trace::InstRecord *traceData) const 3912935Sksewell@umich.edu { 3922935Sksewell@umich.edu Fault fault = NoFault; 3932935Sksewell@umich.edu 3942935Sksewell@umich.edu %(fp_enable_check)s; 3952935Sksewell@umich.edu %(op_dest_decl)s; 3962935Sksewell@umich.edu 3974055Ssaidi@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 3982239SN/A 3992239SN/A if (fault == NoFault) { 4002239SN/A %(postacc_code)s; 4012239SN/A } 4022239SN/A 4032239SN/A if (fault == NoFault) { 4042239SN/A %(op_wb)s; 4052239SN/A } 4062239SN/A 4072124SN/A return fault; 4082124SN/A } 4092124SN/A}}; 4102124SN/A 4112686Sksewell@umich.edudef template MiscExecute {{ 41212234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 4132686Sksewell@umich.edu Trace::InstRecord *traceData) const 4142686Sksewell@umich.edu { 4157725SAli.Saidi@ARM.com Addr EA M5_VAR_USED = 0; 4162686Sksewell@umich.edu Fault fault = NoFault; 4172686Sksewell@umich.edu 4182686Sksewell@umich.edu %(fp_enable_check)s; 4192686Sksewell@umich.edu %(op_decl)s; 4202686Sksewell@umich.edu %(op_rd)s; 4212686Sksewell@umich.edu %(ea_code)s; 4222686Sksewell@umich.edu 4232686Sksewell@umich.edu if (fault == NoFault) { 4242686Sksewell@umich.edu %(memacc_code)s; 4252686Sksewell@umich.edu } 4262686Sksewell@umich.edu 4272686Sksewell@umich.edu return NoFault; 4282686Sksewell@umich.edu } 4292686Sksewell@umich.edu}}; 4302686Sksewell@umich.edu 4312686Sksewell@umich.edudef template MiscInitiateAcc {{ 43212234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 4332686Sksewell@umich.edu Trace::InstRecord *traceData) const 4342686Sksewell@umich.edu { 4352686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4362686Sksewell@umich.edu return NoFault; 4372686Sksewell@umich.edu } 4382686Sksewell@umich.edu}}; 4392686Sksewell@umich.edu 4402686Sksewell@umich.edu 4412686Sksewell@umich.edudef template MiscCompleteAcc {{ 44212234Sgabeblack@google.com Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, 4432686Sksewell@umich.edu Trace::InstRecord *traceData) const 4442686Sksewell@umich.edu { 4452686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4462686Sksewell@umich.edu 4472686Sksewell@umich.edu return NoFault; 4482686Sksewell@umich.edu } 4492686Sksewell@umich.edu}}; 4502686Sksewell@umich.edu 4512124SN/Adef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4522124SN/A mem_flags = [], inst_flags = []) {{ 4532124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4542124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4552750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 4562124SN/A exec_template_base = 'Load') 4572124SN/A}}; 4582124SN/A 4595222Sksewell@umich.edu 4602124SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4612124SN/A mem_flags = [], inst_flags = []) {{ 4622124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4632124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4642124SN/A exec_template_base = 'Store') 4652124SN/A}}; 4662124SN/A 4672686Sksewell@umich.edudef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 4682573SN/A mem_flags = [], inst_flags = []) {{ 4695222Sksewell@umich.edu inst_flags += ['IsIndexed'] 4702573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4712573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4722750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 4732573SN/A exec_template_base = 'Load') 4742573SN/A}}; 4752573SN/A 4762686Sksewell@umich.edudef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 4772573SN/A mem_flags = [], inst_flags = []) {{ 4785222Sksewell@umich.edu inst_flags += ['IsIndexed'] 4792573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4802573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4812573SN/A exec_template_base = 'Store') 4822573SN/A}}; 4832573SN/A 4845222Sksewell@umich.edudef format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 4855222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 4865222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 4875222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 4885222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4895222Sksewell@umich.edu decode_template = ImmNopCheckDecode, 4905222Sksewell@umich.edu exec_template_base = 'Load') 4915222Sksewell@umich.edu}}; 4925222Sksewell@umich.edu 4935222Sksewell@umich.edudef format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 4945222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 4955222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 4965222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 4975222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4985222Sksewell@umich.edu exec_template_base = 'Store') 4995222Sksewell@umich.edu}}; 5005222Sksewell@umich.edu 5015222Sksewell@umich.edu 5022686Sksewell@umich.edudef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5032686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5048564Sgblack@eecs.umich.edu decl_code = ''' 5058588Sgblack@eecs.umich.edu uint32_t mem_word = Mem_uw; 5068564Sgblack@eecs.umich.edu uint32_t unalign_addr = Rs + disp; 5078564Sgblack@eecs.umich.edu uint32_t byte_offset = unalign_addr & 3; 5088564Sgblack@eecs.umich.edu if (GuestByteOrder == BigEndianByteOrder) 5098564Sgblack@eecs.umich.edu byte_offset ^= 3; 5108564Sgblack@eecs.umich.edu ''' 5112573SN/A 5122686Sksewell@umich.edu memacc_code = decl_code + memacc_code 5132686Sksewell@umich.edu 5142686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5152686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5162750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5172686Sksewell@umich.edu exec_template_base = 'Load') 5182686Sksewell@umich.edu}}; 5192686Sksewell@umich.edu 5202686Sksewell@umich.edudef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5212686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5228442Sgblack@eecs.umich.edu decl_code = ''' 5238442Sgblack@eecs.umich.edu uint32_t mem_word = 0; 5248442Sgblack@eecs.umich.edu uint32_t unaligned_addr = Rs + disp; 5258442Sgblack@eecs.umich.edu uint32_t byte_offset = unaligned_addr & 3; 5268564Sgblack@eecs.umich.edu if (GuestByteOrder == BigEndianByteOrder) 5278442Sgblack@eecs.umich.edu byte_offset ^= 3; 5288442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags); 5298442Sgblack@eecs.umich.edu ''' 5302686Sksewell@umich.edu memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 5312686Sksewell@umich.edu 5322686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5332686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5342686Sksewell@umich.edu exec_template_base = 'Store') 5352686Sksewell@umich.edu}}; 5362686Sksewell@umich.edu 5372686Sksewell@umich.edudef format Prefetch(ea_code = {{ EA = Rs + disp; }}, 5382686Sksewell@umich.edu mem_flags = [], pf_flags = [], inst_flags = []) {{ 5396739Sgblack@eecs.umich.edu pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 5407725SAli.Saidi@ARM.com pf_inst_flags = inst_flags 5412686Sksewell@umich.edu 5422686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5432686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, 5447725SAli.Saidi@ARM.com 'warn_once("Prefetching not implemented for MIPS\\n");', 5452686Sksewell@umich.edu pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5462686Sksewell@umich.edu 5472686Sksewell@umich.edu}}; 5482686Sksewell@umich.edu 5492686Sksewell@umich.edudef format StoreCond(memacc_code, postacc_code, 5502686Sksewell@umich.edu ea_code = {{ EA = Rs + disp; }}, 5512495SN/A mem_flags = [], inst_flags = []) {{ 5522495SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5532495SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5542935Sksewell@umich.edu postacc_code, exec_template_base = 'StoreCond') 5552495SN/A}}; 556