mem.isa revision 12234
12686Sksewell@umich.edu// -*- mode:c++ -*- 22686Sksewell@umich.edu 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Steve Reinhardt 302706Sksewell@umich.edu// Korey Sewell 312686Sksewell@umich.edu 322686Sksewell@umich.edu//////////////////////////////////////////////////////////////////// 332686Sksewell@umich.edu// 342686Sksewell@umich.edu// Memory-format instructions 352686Sksewell@umich.edu// 362686Sksewell@umich.edu 372686Sksewell@umich.eduoutput header {{ 382741Sksewell@umich.edu /** 392686Sksewell@umich.edu * Base class for general Mips memory-format instructions. 404661Sksewell@umich.edu */ 412686Sksewell@umich.edu class Memory : public MipsStaticInst 422686Sksewell@umich.edu { 432686Sksewell@umich.edu protected: 442686Sksewell@umich.edu /// Memory request flags. See mem_req_base.hh. 454661Sksewell@umich.edu Request::Flags memAccessFlags; 464661Sksewell@umich.edu 472686Sksewell@umich.edu /// Displacement for EA calculation (signed). 482686Sksewell@umich.edu int32_t disp; 492686Sksewell@umich.edu 504661Sksewell@umich.edu /// Constructor 514661Sksewell@umich.edu Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 524661Sksewell@umich.edu : MipsStaticInst(mnem, _machInst, __opClass), 534661Sksewell@umich.edu disp(sext<16>(OFFSET)) 544661Sksewell@umich.edu { 554661Sksewell@umich.edu } 564661Sksewell@umich.edu 574661Sksewell@umich.edu std::string 584661Sksewell@umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 594661Sksewell@umich.edu }; 604661Sksewell@umich.edu 614661Sksewell@umich.edu /** 624661Sksewell@umich.edu * Base class for a few miscellaneous memory-format insts 634661Sksewell@umich.edu * that don't interpret the disp field 644661Sksewell@umich.edu */ 654661Sksewell@umich.edu class MemoryNoDisp : public Memory 664661Sksewell@umich.edu { 672686Sksewell@umich.edu protected: 682686Sksewell@umich.edu /// Constructor 692686Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 702686Sksewell@umich.edu : Memory(mnem, _machInst, __opClass) 714661Sksewell@umich.edu { 724661Sksewell@umich.edu } 734661Sksewell@umich.edu 744661Sksewell@umich.edu std::string 755222Sksewell@umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 764661Sksewell@umich.edu }; 775222Sksewell@umich.edu}}; 784661Sksewell@umich.edu 794661Sksewell@umich.edu 804661Sksewell@umich.eduoutput decoder {{ 814661Sksewell@umich.edu std::string 824661Sksewell@umich.edu Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 834661Sksewell@umich.edu { 844661Sksewell@umich.edu return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 854661Sksewell@umich.edu flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 864661Sksewell@umich.edu } 874661Sksewell@umich.edu 884661Sksewell@umich.edu std::string 894661Sksewell@umich.edu MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 904661Sksewell@umich.edu { 914661Sksewell@umich.edu return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 924661Sksewell@umich.edu flags[IsFloating] ? 'f' : 'r', 934661Sksewell@umich.edu flags[IsFloating] ? FD : RD, 944661Sksewell@umich.edu RS, RT); 954661Sksewell@umich.edu } 964661Sksewell@umich.edu 974661Sksewell@umich.edu}}; 984661Sksewell@umich.edu 995222Sksewell@umich.eduoutput header {{ 1004661Sksewell@umich.edu uint64_t getMemData(ExecContext *xc, Packet *packet); 1014661Sksewell@umich.edu 1024661Sksewell@umich.edu}}; 1034661Sksewell@umich.edu 1044661Sksewell@umich.eduoutput exec {{ 1052686Sksewell@umich.edu /** return data in cases where there the size of data is only 1064661Sksewell@umich.edu known in the packet 1074661Sksewell@umich.edu */ 1084661Sksewell@umich.edu uint64_t getMemData(ExecContext *xc, Packet *packet) { 1094661Sksewell@umich.edu switch (packet->getSize()) 1104661Sksewell@umich.edu { 1114661Sksewell@umich.edu case 1: 1124661Sksewell@umich.edu return packet->get<uint8_t>(); 1134661Sksewell@umich.edu 1144661Sksewell@umich.edu case 2: 1154661Sksewell@umich.edu return packet->get<uint16_t>(); 1164661Sksewell@umich.edu 1174661Sksewell@umich.edu case 4: 1184661Sksewell@umich.edu return packet->get<uint32_t>(); 1194661Sksewell@umich.edu 1204661Sksewell@umich.edu case 8: 1214661Sksewell@umich.edu return packet->get<uint64_t>(); 1224661Sksewell@umich.edu 1234661Sksewell@umich.edu default: 1244661Sksewell@umich.edu std::cerr << "bad store data size = " << packet->getSize() << std::endl; 1254661Sksewell@umich.edu 1264661Sksewell@umich.edu assert(0); 1274661Sksewell@umich.edu return 0; 1284661Sksewell@umich.edu } 1294661Sksewell@umich.edu } 1304661Sksewell@umich.edu 1314661Sksewell@umich.edu 1324661Sksewell@umich.edu}}; 1334661Sksewell@umich.edu 1344661Sksewell@umich.edudef template LoadStoreDeclare {{ 1354661Sksewell@umich.edu /** 1364661Sksewell@umich.edu * Static instruction class for "%(mnemonic)s". 1374661Sksewell@umich.edu */ 1385222Sksewell@umich.edu class %(class_name)s : public %(base_class)s 1394661Sksewell@umich.edu { 1404661Sksewell@umich.edu public: 1414661Sksewell@umich.edu 1424661Sksewell@umich.edu /// Constructor. 1434661Sksewell@umich.edu %(class_name)s(ExtMachInst machInst); 1444661Sksewell@umich.edu 1454661Sksewell@umich.edu %(BasicExecDeclare)s 1464661Sksewell@umich.edu 1472686Sksewell@umich.edu %(EACompDeclare)s 1482686Sksewell@umich.edu 1492686Sksewell@umich.edu %(InitiateAccDeclare)s 1504661Sksewell@umich.edu 1512686Sksewell@umich.edu %(CompleteAccDeclare)s 1522686Sksewell@umich.edu }; 1534661Sksewell@umich.edu}}; 1544661Sksewell@umich.edu 1554661Sksewell@umich.edudef template EACompDeclare {{ 1562686Sksewell@umich.edu Fault eaComp(ExecContext *, Trace::InstRecord *) const; 1574661Sksewell@umich.edu}}; 1584661Sksewell@umich.edu 1594661Sksewell@umich.edudef template InitiateAccDeclare {{ 1604661Sksewell@umich.edu Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 1614661Sksewell@umich.edu}}; 1624661Sksewell@umich.edu 1634661Sksewell@umich.edu 1644661Sksewell@umich.edudef template CompleteAccDeclare {{ 1654661Sksewell@umich.edu Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const; 1664661Sksewell@umich.edu}}; 1674661Sksewell@umich.edu 1685222Sksewell@umich.edudef template LoadStoreConstructor {{ 1694661Sksewell@umich.edu %(class_name)s::%(class_name)s(ExtMachInst machInst) 1704661Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1714661Sksewell@umich.edu { 1724661Sksewell@umich.edu %(constructor)s; 1734661Sksewell@umich.edu } 1744661Sksewell@umich.edu}}; 1754661Sksewell@umich.edu 1762686Sksewell@umich.edu 1772686Sksewell@umich.edudef template EACompExecute {{ 1782686Sksewell@umich.edu Fault 1792686Sksewell@umich.edu %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const 1804661Sksewell@umich.edu { 1814661Sksewell@umich.edu Addr EA; 1824661Sksewell@umich.edu Fault fault = NoFault; 1834661Sksewell@umich.edu 1844661Sksewell@umich.edu if (this->isFloating()) { 1854661Sksewell@umich.edu %(fp_enable_check)s; 1864661Sksewell@umich.edu 1874661Sksewell@umich.edu if(fault != NoFault) 1884661Sksewell@umich.edu return fault; 1894661Sksewell@umich.edu } 1904661Sksewell@umich.edu 1912686Sksewell@umich.edu %(op_decl)s; 1922686Sksewell@umich.edu %(op_rd)s; 1932686Sksewell@umich.edu %(ea_code)s; 1944661Sksewell@umich.edu 1952686Sksewell@umich.edu // NOTE: Trace Data is written using execute or completeAcc templates 1964661Sksewell@umich.edu if (fault == NoFault) { 1974661Sksewell@umich.edu xc->setEA(EA); 1984661Sksewell@umich.edu } 1994661Sksewell@umich.edu 2004661Sksewell@umich.edu return fault; 2014661Sksewell@umich.edu } 2024661Sksewell@umich.edu}}; 2034661Sksewell@umich.edu 2044661Sksewell@umich.edudef template LoadExecute {{ 2054661Sksewell@umich.edu Fault %(class_name)s::execute(ExecContext *xc, 2064661Sksewell@umich.edu Trace::InstRecord *traceData) const 2074661Sksewell@umich.edu { 2084661Sksewell@umich.edu Addr EA; 2094661Sksewell@umich.edu Fault fault = NoFault; 2104661Sksewell@umich.edu 2114661Sksewell@umich.edu if (this->isFloating()) { 2124661Sksewell@umich.edu %(fp_enable_check)s; 2134661Sksewell@umich.edu 2144661Sksewell@umich.edu if(fault != NoFault) 2154661Sksewell@umich.edu return fault; 2164661Sksewell@umich.edu } 2174661Sksewell@umich.edu 2184661Sksewell@umich.edu %(op_decl)s; 2194661Sksewell@umich.edu %(op_rd)s; 2204661Sksewell@umich.edu %(ea_code)s; 2214661Sksewell@umich.edu 222 if (fault == NoFault) { 223 fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 224 %(memacc_code)s; 225 } 226 227 if (fault == NoFault) { 228 %(op_wb)s; 229 } 230 231 return fault; 232 } 233}}; 234 235 236def template LoadInitiateAcc {{ 237 Fault %(class_name)s::initiateAcc(ExecContext *xc, 238 Trace::InstRecord *traceData) const 239 { 240 Addr EA; 241 Fault fault = NoFault; 242 243 if (this->isFloating()) { 244 %(fp_enable_check)s; 245 246 if(fault != NoFault) 247 return fault; 248 } 249 250 %(op_src_decl)s; 251 %(op_rd)s; 252 %(ea_code)s; 253 254 if (fault == NoFault) { 255 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); 256 } 257 258 return fault; 259 } 260}}; 261 262def template LoadCompleteAcc {{ 263 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, 264 Trace::InstRecord *traceData) const 265 { 266 Fault fault = NoFault; 267 268 if (this->isFloating()) { 269 %(fp_enable_check)s; 270 271 if(fault != NoFault) 272 return fault; 273 } 274 275 %(op_decl)s; 276 %(op_rd)s; 277 278 getMem(pkt, Mem, traceData); 279 280 if (fault == NoFault) { 281 %(memacc_code)s; 282 } 283 284 if (fault == NoFault) { 285 %(op_wb)s; 286 } 287 288 return fault; 289 } 290}}; 291 292def template StoreExecute {{ 293 Fault %(class_name)s::execute(ExecContext *xc, 294 Trace::InstRecord *traceData) const 295 { 296 Addr EA; 297 Fault fault = NoFault; 298 299 %(fp_enable_check)s; 300 %(op_decl)s; 301 %(op_rd)s; 302 %(ea_code)s; 303 304 if (fault == NoFault) { 305 %(memacc_code)s; 306 } 307 308 if (fault == NoFault) { 309 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 310 NULL); 311 } 312 313 if (fault == NoFault) { 314 %(postacc_code)s; 315 } 316 317 if (fault == NoFault) { 318 %(op_wb)s; 319 } 320 321 return fault; 322 } 323}}; 324 325 326def template StoreFPExecute {{ 327 Fault %(class_name)s::execute(ExecContext *xc, 328 Trace::InstRecord *traceData) const 329 { 330 Addr EA; 331 Fault fault = NoFault; 332 333 %(fp_enable_check)s; 334 if(fault != NoFault) 335 return fault; 336 %(op_decl)s; 337 %(op_rd)s; 338 %(ea_code)s; 339 340 if (fault == NoFault) { 341 %(memacc_code)s; 342 } 343 344 if (fault == NoFault) { 345 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 346 NULL); 347 } 348 349 if (fault == NoFault) { 350 %(postacc_code)s; 351 } 352 353 if (fault == NoFault) { 354 %(op_wb)s; 355 } 356 357 return fault; 358 } 359}}; 360 361def template StoreCondExecute {{ 362 Fault %(class_name)s::execute(ExecContext *xc, 363 Trace::InstRecord *traceData) const 364 { 365 Addr EA; 366 Fault fault = NoFault; 367 uint64_t write_result = 0; 368 369 %(fp_enable_check)s; 370 %(op_decl)s; 371 %(op_rd)s; 372 %(ea_code)s; 373 374 if (fault == NoFault) { 375 %(memacc_code)s; 376 } 377 378 if (fault == NoFault) { 379 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 380 &write_result); 381 } 382 383 if (fault == NoFault) { 384 %(postacc_code)s; 385 } 386 387 if (fault == NoFault) { 388 %(op_wb)s; 389 } 390 391 return fault; 392 } 393}}; 394 395def template StoreInitiateAcc {{ 396 Fault %(class_name)s::initiateAcc(ExecContext *xc, 397 Trace::InstRecord *traceData) const 398 { 399 Addr EA; 400 Fault fault = NoFault; 401 402 %(fp_enable_check)s; 403 %(op_decl)s; 404 %(op_rd)s; 405 %(ea_code)s; 406 407 if (fault == NoFault) { 408 %(memacc_code)s; 409 } 410 411 if (fault == NoFault) { 412 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 413 NULL); 414 } 415 416 return fault; 417 } 418}}; 419 420 421def template StoreCompleteAcc {{ 422 Fault %(class_name)s::completeAcc(Packet *pkt, 423 ExecContext *xc, 424 Trace::InstRecord *traceData) const 425 { 426 return NoFault; 427 } 428}}; 429 430def template StoreCondCompleteAcc {{ 431 Fault %(class_name)s::completeAcc(Packet *pkt, 432 ExecContext *xc, 433 Trace::InstRecord *traceData) const 434 { 435 Fault fault = NoFault; 436 437 %(fp_enable_check)s; 438 %(op_dest_decl)s; 439 440 uint64_t write_result = pkt->req->getExtraData(); 441 442 if (fault == NoFault) { 443 %(postacc_code)s; 444 } 445 446 if (fault == NoFault) { 447 %(op_wb)s; 448 } 449 450 return fault; 451 } 452}}; 453 454def template MiscExecute {{ 455 Fault %(class_name)s::execute(ExecContext *xc, 456 Trace::InstRecord *traceData) const 457 { 458 Addr EA M5_VAR_USED = 0; 459 Fault fault = NoFault; 460 461 %(fp_enable_check)s; 462 %(op_decl)s; 463 %(op_rd)s; 464 %(ea_code)s; 465 466 if (fault == NoFault) { 467 %(memacc_code)s; 468 } 469 470 return NoFault; 471 } 472}}; 473 474def template MiscInitiateAcc {{ 475 Fault %(class_name)s::initiateAcc(ExecContext *xc, 476 Trace::InstRecord *traceData) const 477 { 478 panic("Misc instruction does not support split access method!"); 479 return NoFault; 480 } 481}}; 482 483 484def template MiscCompleteAcc {{ 485 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, 486 Trace::InstRecord *traceData) const 487 { 488 panic("Misc instruction does not support split access method!"); 489 490 return NoFault; 491 } 492}}; 493 494def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 495 mem_flags = [], inst_flags = []) {{ 496 (header_output, decoder_output, decode_block, exec_output) = \ 497 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 498 decode_template = ImmNopCheckDecode, 499 exec_template_base = 'Load') 500}}; 501 502 503def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 504 mem_flags = [], inst_flags = []) {{ 505 (header_output, decoder_output, decode_block, exec_output) = \ 506 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 507 exec_template_base = 'Store') 508}}; 509 510def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 511 mem_flags = [], inst_flags = []) {{ 512 inst_flags += ['IsIndexed'] 513 (header_output, decoder_output, decode_block, exec_output) = \ 514 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 515 decode_template = ImmNopCheckDecode, 516 exec_template_base = 'Load') 517}}; 518 519def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 520 mem_flags = [], inst_flags = []) {{ 521 inst_flags += ['IsIndexed'] 522 (header_output, decoder_output, decode_block, exec_output) = \ 523 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 524 exec_template_base = 'Store') 525}}; 526 527def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 528 mem_flags = [], inst_flags = []) {{ 529 inst_flags += ['IsIndexed', 'IsFloating'] 530 (header_output, decoder_output, decode_block, exec_output) = \ 531 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 532 decode_template = ImmNopCheckDecode, 533 exec_template_base = 'Load') 534}}; 535 536def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 537 mem_flags = [], inst_flags = []) {{ 538 inst_flags += ['IsIndexed', 'IsFloating'] 539 (header_output, decoder_output, decode_block, exec_output) = \ 540 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 541 exec_template_base = 'Store') 542}}; 543 544 545def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 546 mem_flags = [], inst_flags = []) {{ 547 decl_code = ''' 548 uint32_t mem_word = Mem_uw; 549 uint32_t unalign_addr = Rs + disp; 550 uint32_t byte_offset = unalign_addr & 3; 551 if (GuestByteOrder == BigEndianByteOrder) 552 byte_offset ^= 3; 553 ''' 554 555 memacc_code = decl_code + memacc_code 556 557 (header_output, decoder_output, decode_block, exec_output) = \ 558 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 559 decode_template = ImmNopCheckDecode, 560 exec_template_base = 'Load') 561}}; 562 563def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 564 mem_flags = [], inst_flags = []) {{ 565 decl_code = ''' 566 uint32_t mem_word = 0; 567 uint32_t unaligned_addr = Rs + disp; 568 uint32_t byte_offset = unaligned_addr & 3; 569 if (GuestByteOrder == BigEndianByteOrder) 570 byte_offset ^= 3; 571 fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags); 572 ''' 573 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 574 575 (header_output, decoder_output, decode_block, exec_output) = \ 576 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 577 exec_template_base = 'Store') 578}}; 579 580def format Prefetch(ea_code = {{ EA = Rs + disp; }}, 581 mem_flags = [], pf_flags = [], inst_flags = []) {{ 582 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 583 pf_inst_flags = inst_flags 584 585 (header_output, decoder_output, decode_block, exec_output) = \ 586 LoadStoreBase(name, Name, ea_code, 587 'warn_once("Prefetching not implemented for MIPS\\n");', 588 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 589 590}}; 591 592def format StoreCond(memacc_code, postacc_code, 593 ea_code = {{ EA = Rs + disp; }}, 594 mem_flags = [], inst_flags = []) {{ 595 (header_output, decoder_output, decode_block, exec_output) = \ 596 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 597 postacc_code, exec_template_base = 'StoreCond') 598}}; 599