mem.isa revision 10196
12124SN/A// -*- mode:c++ -*-
22124SN/A
35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc.
45268Sksewell@umich.edu// All rights reserved.
55268Sksewell@umich.edu//
65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without
75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are
85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright
95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer;
105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright
115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the
125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution;
135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its
145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from
155268Sksewell@umich.edu// this software without specific prior written permission.
165268Sksewell@umich.edu//
175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
285268Sksewell@umich.edu//
295268Sksewell@umich.edu// Authors: Steve Reinhardt
305268Sksewell@umich.edu//          Korey Sewell
312022SN/A
322649Ssaidi@eecs.umich.edu////////////////////////////////////////////////////////////////////
332649Ssaidi@eecs.umich.edu//
342706Sksewell@umich.edu// Memory-format instructions
352649Ssaidi@eecs.umich.edu//
362649Ssaidi@eecs.umich.edu
372022SN/Aoutput header {{
382124SN/A    /**
392124SN/A     * Base class for general Mips memory-format instructions.
402124SN/A     */
412124SN/A    class Memory : public MipsStaticInst
422124SN/A    {
432124SN/A      protected:
442124SN/A        /// Memory request flags.  See mem_req_base.hh.
455736Snate@binkert.org        Request::Flags memAccessFlags;
462239SN/A
472124SN/A        /// Displacement for EA calculation (signed).
482124SN/A        int32_t disp;
492124SN/A
502124SN/A        /// Constructor
516207Sksewell@umich.edu        Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
522124SN/A            : MipsStaticInst(mnem, _machInst, __opClass),
532742Sksewell@umich.edu              disp(sext<16>(OFFSET))
542022SN/A        {
552124SN/A        }
562022SN/A
572124SN/A        std::string
582124SN/A        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
592124SN/A    };
602124SN/A
612742Sksewell@umich.edu     /**
622742Sksewell@umich.edu     * Base class for a few miscellaneous memory-format insts
632742Sksewell@umich.edu     * that don't interpret the disp field
642742Sksewell@umich.edu     */
652742Sksewell@umich.edu    class MemoryNoDisp : public Memory
662742Sksewell@umich.edu    {
672742Sksewell@umich.edu      protected:
682742Sksewell@umich.edu        /// Constructor
696207Sksewell@umich.edu        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
706207Sksewell@umich.edu            : Memory(mnem, _machInst, __opClass)
712742Sksewell@umich.edu        {
722742Sksewell@umich.edu        }
732742Sksewell@umich.edu
742742Sksewell@umich.edu        std::string
752742Sksewell@umich.edu        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
762742Sksewell@umich.edu    };
772022SN/A}};
782022SN/A
792124SN/A
802022SN/Aoutput decoder {{
812124SN/A    std::string
822124SN/A    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
832124SN/A    {
842742Sksewell@umich.edu        return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
852239SN/A                        flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
862124SN/A    }
872124SN/A
882742Sksewell@umich.edu    std::string
892742Sksewell@umich.edu    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
902742Sksewell@umich.edu    {
912742Sksewell@umich.edu        return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
922742Sksewell@umich.edu                        flags[IsFloating] ? 'f' : 'r',
932742Sksewell@umich.edu                        flags[IsFloating] ? FD : RD,
942742Sksewell@umich.edu                        RS, RT);
952742Sksewell@umich.edu    }
964661Sksewell@umich.edu
974661Sksewell@umich.edu}};
984661Sksewell@umich.edu
999554Sandreas.hansson@arm.comoutput header {{
1009554Sandreas.hansson@arm.com    uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet);
1019554Sandreas.hansson@arm.com
1029554Sandreas.hansson@arm.com}};
1039554Sandreas.hansson@arm.com
1044661Sksewell@umich.eduoutput exec {{
1054661Sksewell@umich.edu    /** return data in cases where there the size of data is only
1064661Sksewell@umich.edu        known in the packet
1074661Sksewell@umich.edu    */
10810196SCurtis.Dunham@arm.com    uint64_t getMemData(CPU_EXEC_CONTEXT *xc, Packet *packet) {
1094661Sksewell@umich.edu        switch (packet->getSize())
1104661Sksewell@umich.edu        {
1115222Sksewell@umich.edu          case 1:
1124661Sksewell@umich.edu            return packet->get<uint8_t>();
1134661Sksewell@umich.edu
1145222Sksewell@umich.edu          case 2:
1154661Sksewell@umich.edu            return packet->get<uint16_t>();
1164661Sksewell@umich.edu
1175222Sksewell@umich.edu          case 4:
1184661Sksewell@umich.edu            return packet->get<uint32_t>();
1194661Sksewell@umich.edu
1205222Sksewell@umich.edu          case 8:
1214661Sksewell@umich.edu            return packet->get<uint64_t>();
1224661Sksewell@umich.edu
1234661Sksewell@umich.edu          default:
1244661Sksewell@umich.edu            std::cerr << "bad store data size = " << packet->getSize() << std::endl;
1254661Sksewell@umich.edu
1264661Sksewell@umich.edu            assert(0);
1274661Sksewell@umich.edu            return 0;
1284661Sksewell@umich.edu        }
1294661Sksewell@umich.edu    }
1304661Sksewell@umich.edu
1314661Sksewell@umich.edu
1322022SN/A}};
1332022SN/A
1342124SN/Adef template LoadStoreDeclare {{
1352124SN/A    /**
1362124SN/A     * Static instruction class for "%(mnemonic)s".
1372124SN/A     */
1382124SN/A    class %(class_name)s : public %(base_class)s
1392124SN/A    {
1402124SN/A      public:
1412124SN/A
1422124SN/A        /// Constructor.
1434661Sksewell@umich.edu        %(class_name)s(ExtMachInst machInst);
1442124SN/A
1452124SN/A        %(BasicExecDeclare)s
1462124SN/A
1476207Sksewell@umich.edu        %(EACompDeclare)s
1486207Sksewell@umich.edu
1492124SN/A        %(InitiateAccDeclare)s
1502124SN/A
1512124SN/A        %(CompleteAccDeclare)s
1522124SN/A    };
1532022SN/A}};
1542022SN/A
1556207Sksewell@umich.edudef template EACompDeclare {{
1566207Sksewell@umich.edu    Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
1576207Sksewell@umich.edu}};
1582124SN/A
1592124SN/Adef template InitiateAccDeclare {{
1602132SN/A    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
1612022SN/A}};
1622124SN/A
1632124SN/A
1642124SN/Adef template CompleteAccDeclare {{
1654661Sksewell@umich.edu    Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
1662124SN/A}};
1672124SN/A
1686207Sksewell@umich.edudef template LoadStoreConstructor {{
16910184SCurtis.Dunham@arm.com    %(class_name)s::%(class_name)s(ExtMachInst machInst)
1706207Sksewell@umich.edu         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
1712124SN/A    {
1723953Sstever@eecs.umich.edu        %(constructor)s;
1732124SN/A    }
1743953Sstever@eecs.umich.edu}};
1752124SN/A
1763953Sstever@eecs.umich.edu
1772124SN/Adef template EACompExecute {{
1782132SN/A    Fault
17910196SCurtis.Dunham@arm.com    %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
1802124SN/A                                   Trace::InstRecord *traceData) const
1812124SN/A    {
1822124SN/A        Addr EA;
1832132SN/A        Fault fault = NoFault;
1842124SN/A
1855222Sksewell@umich.edu        if (this->isFloating()) {
1865222Sksewell@umich.edu            %(fp_enable_check)s;
1875222Sksewell@umich.edu
1885222Sksewell@umich.edu            if(fault != NoFault)
1895222Sksewell@umich.edu                return fault;
1905222Sksewell@umich.edu        }
1915222Sksewell@umich.edu
1922124SN/A        %(op_decl)s;
1932124SN/A        %(op_rd)s;
1943953Sstever@eecs.umich.edu        %(ea_code)s;
1952124SN/A
1964661Sksewell@umich.edu        // NOTE: Trace Data is written using execute or completeAcc templates
1972124SN/A        if (fault == NoFault) {
1982124SN/A            xc->setEA(EA);
1992124SN/A        }
2002124SN/A
2012124SN/A        return fault;
2022124SN/A    }
2032124SN/A}};
2042124SN/A
2052124SN/Adef template LoadExecute {{
20610196SCurtis.Dunham@arm.com    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
2072124SN/A                                  Trace::InstRecord *traceData) const
2082124SN/A    {
2092124SN/A        Addr EA;
2102132SN/A        Fault fault = NoFault;
2112124SN/A
2125222Sksewell@umich.edu        if (this->isFloating()) {
2135222Sksewell@umich.edu            %(fp_enable_check)s;
2145222Sksewell@umich.edu
2155222Sksewell@umich.edu            if(fault != NoFault)
2165222Sksewell@umich.edu                return fault;
2175222Sksewell@umich.edu        }
2185222Sksewell@umich.edu
2192124SN/A        %(op_decl)s;
2202124SN/A        %(op_rd)s;
2212124SN/A        %(ea_code)s;
2222124SN/A
2232124SN/A        if (fault == NoFault) {
2248442Sgblack@eecs.umich.edu            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
2252124SN/A            %(memacc_code)s;
2262124SN/A        }
2272124SN/A
2282124SN/A        if (fault == NoFault) {
2292124SN/A            %(op_wb)s;
2302124SN/A        }
2312124SN/A
2322124SN/A        return fault;
2332124SN/A    }
2342124SN/A}};
2352124SN/A
2362124SN/A
2372124SN/Adef template LoadInitiateAcc {{
23810196SCurtis.Dunham@arm.com    Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
2392124SN/A                                      Trace::InstRecord *traceData) const
2402124SN/A    {
2412239SN/A        Addr EA;
2422132SN/A        Fault fault = NoFault;
2432239SN/A
2445222Sksewell@umich.edu        if (this->isFloating()) {
2455222Sksewell@umich.edu            %(fp_enable_check)s;
2465222Sksewell@umich.edu
2475222Sksewell@umich.edu            if(fault != NoFault)
2485222Sksewell@umich.edu                return fault;
2495222Sksewell@umich.edu        }
2505222Sksewell@umich.edu
2512239SN/A        %(op_src_decl)s;
2522239SN/A        %(op_rd)s;
2532239SN/A        %(ea_code)s;
2542239SN/A
2552239SN/A        if (fault == NoFault) {
2568442Sgblack@eecs.umich.edu            fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
2572239SN/A        }
2582239SN/A
2592124SN/A        return fault;
2602124SN/A    }
2612124SN/A}};
2622124SN/A
2632124SN/Adef template LoadCompleteAcc {{
2644661Sksewell@umich.edu    Fault %(class_name)s::completeAcc(Packet *pkt,
26510196SCurtis.Dunham@arm.com                                      CPU_EXEC_CONTEXT *xc,
2662124SN/A                                      Trace::InstRecord *traceData) const
2672124SN/A    {
2682132SN/A        Fault fault = NoFault;
2692239SN/A
2705222Sksewell@umich.edu        if (this->isFloating()) {
2715222Sksewell@umich.edu            %(fp_enable_check)s;
2725222Sksewell@umich.edu
2735222Sksewell@umich.edu            if(fault != NoFault)
2745222Sksewell@umich.edu                return fault;
2755222Sksewell@umich.edu        }
2765222Sksewell@umich.edu
2772506SN/A        %(op_decl)s;
2784661Sksewell@umich.edu        %(op_rd)s;
2792239SN/A
2808442Sgblack@eecs.umich.edu        getMem(pkt, Mem, traceData);
2812239SN/A
2822239SN/A        if (fault == NoFault) {
2832239SN/A            %(memacc_code)s;
2842239SN/A        }
2852239SN/A
2862239SN/A        if (fault == NoFault) {
2872239SN/A            %(op_wb)s;
2882239SN/A        }
2892239SN/A
2902124SN/A        return fault;
2912124SN/A    }
2922124SN/A}};
2932124SN/A
2942124SN/Adef template StoreExecute {{
29510196SCurtis.Dunham@arm.com    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
2962124SN/A                                  Trace::InstRecord *traceData) const
2972124SN/A    {
2982124SN/A        Addr EA;
2992132SN/A        Fault fault = NoFault;
3004056Sstever@eecs.umich.edu
3014056Sstever@eecs.umich.edu        %(fp_enable_check)s;
3024056Sstever@eecs.umich.edu        %(op_decl)s;
3034056Sstever@eecs.umich.edu        %(op_rd)s;
3044056Sstever@eecs.umich.edu        %(ea_code)s;
3054056Sstever@eecs.umich.edu
3064056Sstever@eecs.umich.edu        if (fault == NoFault) {
3074056Sstever@eecs.umich.edu            %(memacc_code)s;
3084056Sstever@eecs.umich.edu        }
3094056Sstever@eecs.umich.edu
3104056Sstever@eecs.umich.edu        if (fault == NoFault) {
3118442Sgblack@eecs.umich.edu            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
3128442Sgblack@eecs.umich.edu                    NULL);
3134056Sstever@eecs.umich.edu        }
3144056Sstever@eecs.umich.edu
3154056Sstever@eecs.umich.edu        if (fault == NoFault) {
3164056Sstever@eecs.umich.edu            %(postacc_code)s;
3174056Sstever@eecs.umich.edu        }
3184056Sstever@eecs.umich.edu
3194056Sstever@eecs.umich.edu        if (fault == NoFault) {
3204056Sstever@eecs.umich.edu            %(op_wb)s;
3214056Sstever@eecs.umich.edu        }
3224056Sstever@eecs.umich.edu
3234056Sstever@eecs.umich.edu        return fault;
3244056Sstever@eecs.umich.edu    }
3254056Sstever@eecs.umich.edu}};
3264056Sstever@eecs.umich.edu
3275222Sksewell@umich.edu
3285222Sksewell@umich.edudef template StoreFPExecute {{
32910196SCurtis.Dunham@arm.com    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
3305222Sksewell@umich.edu                                  Trace::InstRecord *traceData) const
3315222Sksewell@umich.edu    {
3325222Sksewell@umich.edu        Addr EA;
3335222Sksewell@umich.edu        Fault fault = NoFault;
3345222Sksewell@umich.edu
3355222Sksewell@umich.edu        %(fp_enable_check)s;
3365222Sksewell@umich.edu        if(fault != NoFault)
3375222Sksewell@umich.edu          return fault;
3385222Sksewell@umich.edu        %(op_decl)s;
3395222Sksewell@umich.edu        %(op_rd)s;
3405222Sksewell@umich.edu        %(ea_code)s;
3415222Sksewell@umich.edu
3425222Sksewell@umich.edu        if (fault == NoFault) {
3435222Sksewell@umich.edu            %(memacc_code)s;
3445222Sksewell@umich.edu        }
3455222Sksewell@umich.edu
3465222Sksewell@umich.edu        if (fault == NoFault) {
3478442Sgblack@eecs.umich.edu            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
3488442Sgblack@eecs.umich.edu                    NULL);
3495222Sksewell@umich.edu        }
3505222Sksewell@umich.edu
3515222Sksewell@umich.edu        if (fault == NoFault) {
3525222Sksewell@umich.edu            %(postacc_code)s;
3535222Sksewell@umich.edu        }
3545222Sksewell@umich.edu
3555222Sksewell@umich.edu        if (fault == NoFault) {
3565222Sksewell@umich.edu            %(op_wb)s;
3575222Sksewell@umich.edu        }
3585222Sksewell@umich.edu
3595222Sksewell@umich.edu        return fault;
3605222Sksewell@umich.edu    }
3615222Sksewell@umich.edu}};
3625222Sksewell@umich.edu
3634056Sstever@eecs.umich.edudef template StoreCondExecute {{
36410196SCurtis.Dunham@arm.com    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
3654056Sstever@eecs.umich.edu                                  Trace::InstRecord *traceData) const
3664056Sstever@eecs.umich.edu    {
3674056Sstever@eecs.umich.edu        Addr EA;
3684056Sstever@eecs.umich.edu        Fault fault = NoFault;
3692124SN/A        uint64_t write_result = 0;
3702124SN/A
3712124SN/A        %(fp_enable_check)s;
3722124SN/A        %(op_decl)s;
3732124SN/A        %(op_rd)s;
3742124SN/A        %(ea_code)s;
3752124SN/A
3762124SN/A        if (fault == NoFault) {
3772124SN/A            %(memacc_code)s;
3782124SN/A        }
3792124SN/A
3802124SN/A        if (fault == NoFault) {
3818442Sgblack@eecs.umich.edu            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
3828442Sgblack@eecs.umich.edu                    &write_result);
3832124SN/A        }
3842124SN/A
3852124SN/A        if (fault == NoFault) {
3862124SN/A            %(postacc_code)s;
3872124SN/A        }
3882124SN/A
3892124SN/A        if (fault == NoFault) {
3902124SN/A            %(op_wb)s;
3912124SN/A        }
3922124SN/A
3932124SN/A        return fault;
3942124SN/A    }
3952124SN/A}};
3962124SN/A
3972124SN/Adef template StoreInitiateAcc {{
39810196SCurtis.Dunham@arm.com    Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
3992124SN/A                                      Trace::InstRecord *traceData) const
4002124SN/A    {
4012239SN/A        Addr EA;
4022132SN/A        Fault fault = NoFault;
4032239SN/A
4042239SN/A        %(fp_enable_check)s;
4052506SN/A        %(op_decl)s;
4062239SN/A        %(op_rd)s;
4072239SN/A        %(ea_code)s;
4082239SN/A
4092239SN/A        if (fault == NoFault) {
4102239SN/A            %(memacc_code)s;
4112239SN/A        }
4122239SN/A
4132239SN/A        if (fault == NoFault) {
4148442Sgblack@eecs.umich.edu            fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
4158442Sgblack@eecs.umich.edu                    NULL);
4162239SN/A        }
4172239SN/A
4182124SN/A        return fault;
4192124SN/A    }
4202124SN/A}};
4212124SN/A
4222124SN/A
4232124SN/Adef template StoreCompleteAcc {{
4244661Sksewell@umich.edu    Fault %(class_name)s::completeAcc(Packet *pkt,
42510196SCurtis.Dunham@arm.com                                      CPU_EXEC_CONTEXT *xc,
4262124SN/A                                      Trace::InstRecord *traceData) const
4272124SN/A    {
4287712Sgblack@eecs.umich.edu        return NoFault;
4292935Sksewell@umich.edu    }
4302935Sksewell@umich.edu}};
4312935Sksewell@umich.edu
4322935Sksewell@umich.edudef template StoreCondCompleteAcc {{
4334661Sksewell@umich.edu    Fault %(class_name)s::completeAcc(Packet *pkt,
43410196SCurtis.Dunham@arm.com                                      CPU_EXEC_CONTEXT *xc,
4352935Sksewell@umich.edu                                      Trace::InstRecord *traceData) const
4362935Sksewell@umich.edu    {
4372935Sksewell@umich.edu        Fault fault = NoFault;
4382935Sksewell@umich.edu
4392935Sksewell@umich.edu        %(fp_enable_check)s;
4402935Sksewell@umich.edu        %(op_dest_decl)s;
4412935Sksewell@umich.edu
4424055Ssaidi@eecs.umich.edu        uint64_t write_result = pkt->req->getExtraData();
4432239SN/A
4442239SN/A        if (fault == NoFault) {
4452239SN/A            %(postacc_code)s;
4462239SN/A        }
4472239SN/A
4482239SN/A        if (fault == NoFault) {
4492239SN/A            %(op_wb)s;
4502239SN/A        }
4512239SN/A
4522124SN/A        return fault;
4532124SN/A    }
4542124SN/A}};
4552124SN/A
4562686Sksewell@umich.edudef template MiscExecute {{
45710196SCurtis.Dunham@arm.com    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
4582686Sksewell@umich.edu                                  Trace::InstRecord *traceData) const
4592686Sksewell@umich.edu    {
4607725SAli.Saidi@ARM.com        Addr EA M5_VAR_USED = 0;
4612686Sksewell@umich.edu        Fault fault = NoFault;
4622686Sksewell@umich.edu
4632686Sksewell@umich.edu        %(fp_enable_check)s;
4642686Sksewell@umich.edu        %(op_decl)s;
4652686Sksewell@umich.edu        %(op_rd)s;
4662686Sksewell@umich.edu        %(ea_code)s;
4672686Sksewell@umich.edu
4682686Sksewell@umich.edu        if (fault == NoFault) {
4692686Sksewell@umich.edu            %(memacc_code)s;
4702686Sksewell@umich.edu        }
4712686Sksewell@umich.edu
4722686Sksewell@umich.edu        return NoFault;
4732686Sksewell@umich.edu    }
4742686Sksewell@umich.edu}};
4752686Sksewell@umich.edu
4762686Sksewell@umich.edudef template MiscInitiateAcc {{
47710196SCurtis.Dunham@arm.com    Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
4782686Sksewell@umich.edu                                      Trace::InstRecord *traceData) const
4792686Sksewell@umich.edu    {
4802686Sksewell@umich.edu        panic("Misc instruction does not support split access method!");
4812686Sksewell@umich.edu        return NoFault;
4822686Sksewell@umich.edu    }
4832686Sksewell@umich.edu}};
4842686Sksewell@umich.edu
4852686Sksewell@umich.edu
4862686Sksewell@umich.edudef template MiscCompleteAcc {{
4874661Sksewell@umich.edu    Fault %(class_name)s::completeAcc(Packet *pkt,
48810196SCurtis.Dunham@arm.com                                      CPU_EXEC_CONTEXT *xc,
4892686Sksewell@umich.edu                                      Trace::InstRecord *traceData) const
4902686Sksewell@umich.edu    {
4912686Sksewell@umich.edu        panic("Misc instruction does not support split access method!");
4922686Sksewell@umich.edu
4932686Sksewell@umich.edu        return NoFault;
4942686Sksewell@umich.edu    }
4952686Sksewell@umich.edu}};
4962686Sksewell@umich.edu
4972124SN/Adef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
4982124SN/A                     mem_flags = [], inst_flags = []) {{
4992124SN/A    (header_output, decoder_output, decode_block, exec_output) = \
5002124SN/A        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
5012750Sksewell@umich.edu                      decode_template = ImmNopCheckDecode,
5022124SN/A                      exec_template_base = 'Load')
5032124SN/A}};
5042124SN/A
5055222Sksewell@umich.edu
5062124SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
5072124SN/A                     mem_flags = [], inst_flags = []) {{
5082124SN/A    (header_output, decoder_output, decode_block, exec_output) = \
5092124SN/A        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
5102124SN/A                      exec_template_base = 'Store')
5112124SN/A}};
5122124SN/A
5132686Sksewell@umich.edudef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
5142573SN/A                     mem_flags = [], inst_flags = []) {{
5155222Sksewell@umich.edu    inst_flags += ['IsIndexed']
5162573SN/A    (header_output, decoder_output, decode_block, exec_output) = \
5172573SN/A        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
5182750Sksewell@umich.edu                      decode_template = ImmNopCheckDecode,
5192573SN/A                      exec_template_base = 'Load')
5202573SN/A}};
5212573SN/A
5222686Sksewell@umich.edudef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
5232573SN/A                     mem_flags = [], inst_flags = []) {{
5245222Sksewell@umich.edu    inst_flags += ['IsIndexed']
5252573SN/A    (header_output, decoder_output, decode_block, exec_output) = \
5262573SN/A        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
5272573SN/A                      exec_template_base = 'Store')
5282573SN/A}};
5292573SN/A
5305222Sksewell@umich.edudef format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
5315222Sksewell@umich.edu                     mem_flags = [], inst_flags = []) {{
5325222Sksewell@umich.edu    inst_flags += ['IsIndexed', 'IsFloating']
5335222Sksewell@umich.edu    (header_output, decoder_output, decode_block, exec_output) = \
5345222Sksewell@umich.edu        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
5355222Sksewell@umich.edu                      decode_template = ImmNopCheckDecode,
5365222Sksewell@umich.edu                      exec_template_base = 'Load')
5375222Sksewell@umich.edu}};
5385222Sksewell@umich.edu
5395222Sksewell@umich.edudef format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
5405222Sksewell@umich.edu                     mem_flags = [], inst_flags = []) {{
5415222Sksewell@umich.edu    inst_flags += ['IsIndexed', 'IsFloating']
5425222Sksewell@umich.edu    (header_output, decoder_output, decode_block, exec_output) = \
5435222Sksewell@umich.edu        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
5445222Sksewell@umich.edu                      exec_template_base = 'Store')
5455222Sksewell@umich.edu}};
5465222Sksewell@umich.edu
5475222Sksewell@umich.edu
5482686Sksewell@umich.edudef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
5492686Sksewell@umich.edu                     mem_flags = [], inst_flags = []) {{
5508564Sgblack@eecs.umich.edu    decl_code = '''
5518588Sgblack@eecs.umich.edu        uint32_t mem_word = Mem_uw;
5528564Sgblack@eecs.umich.edu        uint32_t unalign_addr = Rs + disp;
5538564Sgblack@eecs.umich.edu        uint32_t byte_offset = unalign_addr & 3;
5548564Sgblack@eecs.umich.edu        if (GuestByteOrder == BigEndianByteOrder)
5558564Sgblack@eecs.umich.edu            byte_offset ^= 3;
5568564Sgblack@eecs.umich.edu    '''
5572573SN/A
5582686Sksewell@umich.edu    memacc_code = decl_code + memacc_code
5592686Sksewell@umich.edu
5602686Sksewell@umich.edu    (header_output, decoder_output, decode_block, exec_output) = \
5612686Sksewell@umich.edu        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
5622750Sksewell@umich.edu                      decode_template = ImmNopCheckDecode,
5632686Sksewell@umich.edu                      exec_template_base = 'Load')
5642686Sksewell@umich.edu}};
5652686Sksewell@umich.edu
5662686Sksewell@umich.edudef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
5672686Sksewell@umich.edu                     mem_flags = [], inst_flags = []) {{
5688442Sgblack@eecs.umich.edu    decl_code = '''
5698442Sgblack@eecs.umich.edu        uint32_t mem_word = 0;
5708442Sgblack@eecs.umich.edu        uint32_t unaligned_addr = Rs + disp;
5718442Sgblack@eecs.umich.edu        uint32_t byte_offset = unaligned_addr & 3;
5728564Sgblack@eecs.umich.edu        if (GuestByteOrder == BigEndianByteOrder)
5738442Sgblack@eecs.umich.edu            byte_offset ^= 3;
5748442Sgblack@eecs.umich.edu        fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
5758442Sgblack@eecs.umich.edu    '''
5762686Sksewell@umich.edu    memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
5772686Sksewell@umich.edu
5782686Sksewell@umich.edu    (header_output, decoder_output, decode_block, exec_output) = \
5792686Sksewell@umich.edu        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
5802686Sksewell@umich.edu                      exec_template_base = 'Store')
5812686Sksewell@umich.edu}};
5822686Sksewell@umich.edu
5832686Sksewell@umich.edudef format Prefetch(ea_code = {{ EA = Rs + disp; }},
5842686Sksewell@umich.edu                          mem_flags = [], pf_flags = [], inst_flags = []) {{
5856739Sgblack@eecs.umich.edu    pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
5867725SAli.Saidi@ARM.com    pf_inst_flags = inst_flags
5872686Sksewell@umich.edu
5882686Sksewell@umich.edu    (header_output, decoder_output, decode_block, exec_output) = \
5892686Sksewell@umich.edu        LoadStoreBase(name, Name, ea_code,
5907725SAli.Saidi@ARM.com                      'warn_once("Prefetching not implemented for MIPS\\n");',
5912686Sksewell@umich.edu                      pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
5922686Sksewell@umich.edu
5932686Sksewell@umich.edu}};
5942686Sksewell@umich.edu
5952686Sksewell@umich.edudef format StoreCond(memacc_code, postacc_code,
5962686Sksewell@umich.edu                     ea_code = {{ EA = Rs + disp; }},
5972495SN/A                     mem_flags = [], inst_flags = []) {{
5982495SN/A    (header_output, decoder_output, decode_block, exec_output) = \
5992495SN/A        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
6002935Sksewell@umich.edu                      postacc_code, exec_template_base = 'StoreCond')
6012495SN/A}};
602