int.isa revision 2980:eab855f06b79 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Korey Sewell
30
31////////////////////////////////////////////////////////////////////
32//
33// Integer operate instructions
34//
35output header {{
36#include <iostream>
37        /**
38         * Base class for integer operations.
39         */
40        class IntOp : public MipsStaticInst
41        {
42                protected:
43
44                /// Constructor
45                IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
46                                MipsStaticInst(mnem, _machInst, __opClass)
47                {
48                }
49
50                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
51        };
52
53
54        class HiLoOp: public IntOp
55        {
56                protected:
57
58                /// Constructor
59                HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
60                                IntOp(mnem, _machInst, __opClass)
61                {
62                }
63
64                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
65        };
66
67        class HiLoMiscOp: public HiLoOp
68        {
69                protected:
70
71                /// Constructor
72                HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
73                                HiLoOp(mnem, _machInst, __opClass)
74                {
75                }
76
77                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
78        };
79
80
81        class IntImmOp : public MipsStaticInst
82        {
83                protected:
84
85                int16_t imm;
86                int32_t sextImm;
87                uint32_t zextImm;
88
89                /// Constructor
90                IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
91                    MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM),
92                    sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM)
93                {
94                    //If Bit 15 is 1 then Sign Extend
95                    int32_t temp = sextImm & 0x00008000;
96                    if (temp > 0 && mnemonic != "lui") {
97                        sextImm |= 0xFFFF0000;
98                    }
99                }
100
101                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
102
103
104        };
105
106}};
107
108// HiLo<Misc> instruction class execute method template.
109// Mainly to get instruction trace data to print out
110// correctly
111def template HiLoExecute {{
112        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
113        {
114                Fault fault = NoFault;
115
116                %(fp_enable_check)s;
117                %(op_decl)s;
118                %(op_rd)s;
119                %(code)s;
120
121                if(fault == NoFault)
122                {
123                    %(op_wb)s;
124                    //If there are 2 Destination Registers then
125                    //concatenate the values for the traceData
126                    if(traceData && _numDestRegs == 2) {
127                        uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
128                        traceData->setData(hilo_final_val);
129                    }
130                }
131                return fault;
132        }
133}};
134
135//Outputs to decoder.cc
136output decoder {{
137        std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
138        {
139            std::stringstream ss;
140
141            ccprintf(ss, "%-10s ", mnemonic);
142
143            // just print the first dest... if there's a second one,
144            // it's generally implicit
145            if (_numDestRegs > 0) {
146                printReg(ss, _destRegIdx[0]);
147                ss << ", ";
148            }
149
150            // just print the first two source regs... if there's
151            // a third one, it's a read-modify-write dest (Rc),
152            // e.g. for CMOVxx
153            if (_numSrcRegs > 0) {
154                printReg(ss, _srcRegIdx[0]);
155            }
156
157            if (_numSrcRegs > 1) {
158                ss << ", ";
159                printReg(ss, _srcRegIdx[1]);
160            }
161
162            return ss.str();
163        }
164
165        std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
166        {
167            std::stringstream ss;
168
169            ccprintf(ss, "%-10s ", mnemonic);
170
171            //Destination Registers are implicit for HI/LO ops
172            if (_numSrcRegs > 0) {
173                printReg(ss, _srcRegIdx[0]);
174            }
175
176            if (_numSrcRegs > 1) {
177                ss << ", ";
178                printReg(ss, _srcRegIdx[1]);
179            }
180
181            return ss.str();
182        }
183
184        std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
185        {
186            std::stringstream ss;
187
188            ccprintf(ss, "%-10s ", mnemonic);
189
190            if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
191                printReg(ss, _destRegIdx[0]);
192            } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
193                printReg(ss, _srcRegIdx[0]);
194            }
195
196            return ss.str();
197        }
198
199        std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
200        {
201            std::stringstream ss;
202
203            ccprintf(ss, "%-10s ", mnemonic);
204
205            if (_numDestRegs > 0) {
206                printReg(ss, _destRegIdx[0]);
207            }
208
209            ss << ", ";
210
211            if (_numSrcRegs > 0) {
212                printReg(ss, _srcRegIdx[0]);
213                ss << ", ";
214            }
215
216            if( mnemonic == "lui")
217                ccprintf(ss, "0x%x ", sextImm);
218            else
219                ss << (int) sextImm;
220
221            return ss.str();
222        }
223
224}};
225
226def format IntOp(code, *opt_flags) {{
227    iop = InstObjParams(name, Name, 'IntOp', CodeBlock(code), opt_flags)
228    header_output = BasicDeclare.subst(iop)
229    decoder_output = BasicConstructor.subst(iop)
230    decode_block = RegNopCheckDecode.subst(iop)
231    exec_output = BasicExecute.subst(iop)
232}};
233
234def format IntImmOp(code, *opt_flags) {{
235    iop = InstObjParams(name, Name, 'IntImmOp', CodeBlock(code), opt_flags)
236    header_output = BasicDeclare.subst(iop)
237    decoder_output = BasicConstructor.subst(iop)
238    decode_block = ImmNopCheckDecode.subst(iop)
239    exec_output = BasicExecute.subst(iop)
240}};
241
242def format HiLoOp(code, *opt_flags) {{
243    if '.sd' in code:
244        code = 'int64_t ' + code
245    elif '.ud' in code:
246        code = 'uint64_t ' + code
247
248    code += 'HI = val<63:32>;\n'
249    code += 'LO = val<31:0>;\n'
250
251    iop = InstObjParams(name, Name, 'HiLoOp', CodeBlock(code), opt_flags)
252    header_output = BasicDeclare.subst(iop)
253    decoder_output = BasicConstructor.subst(iop)
254    decode_block = BasicDecode.subst(iop)
255    exec_output = HiLoExecute.subst(iop)
256}};
257
258def format HiLoMiscOp(code, *opt_flags) {{
259    iop = InstObjParams(name, Name, 'HiLoMiscOp', CodeBlock(code), opt_flags)
260    header_output = BasicDeclare.subst(iop)
261    decoder_output = BasicConstructor.subst(iop)
262    decode_block = BasicDecode.subst(iop)
263    exec_output = HiLoExecute.subst(iop)
264}};
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